Difference between revisions of "GigaDevice GD32A4"
(→Internal Flash) |
(→Internal Flash) |
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| Main flash Bank 1 || 0x08100000 || Up to 2 MB || style="text-align:center;"| {{YES}} |
| Main flash Bank 1 || 0x08100000 || Up to 2 MB || style="text-align:center;"| {{YES}} |
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| − | | |
+ | | Option Byte Bank 0 || 0x1FFFC000|| 24 B || style="text-align:center;"| {{YES}} |
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| − | | Option Byte |
+ | | Option Byte Bank 1 || 0x1FFEC000|| 4 B || style="text-align:center;"| {{YES}} |
| − | |- |
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| − | | Option Byte 1 || 0x40022068|| 4 B || style="text-align:center;"| {{YES}} |
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| OTP Bytes || 0x1FFF7000 || 1 KB || style="text-align:center;"| {{NO}} |
| OTP Bytes || 0x1FFF7000 || 1 KB || style="text-align:center;"| {{NO}} |
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Revision as of 08:31, 25 June 2024
The GD32A49x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M4 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash Bank 0 | 0x08000000 | Up to 1 MB | 
|
| Main flash Bank 1 | 0x08100000 | Up to 2 MB |
|
| Option Byte Bank 0 | 0x1FFFC000 | 24 B |
|
| Option Byte Bank 1 | 0x1FFEC000 | 4 B |
|
| OTP Bytes | 0x1FFF7000 | 1 KB | 
|
Note:
After changing Option Byte 1, a power on reset has to be performed.
After changing Option Byte 1, a power on reset has to be performed.
ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
