J-Link LITE Cortex-M V9
This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Link LITE Cortex-M V9.
Contents
Hardware Features
Feature | Supported |
---|---|
USB 2.0 Full Speed | |
JTAG interface | |
SWD interface | |
SWO interface | |
SPI interface | |
QSPI interface | |
Microchip ICSP interface | |
Renesas FINE interface | |
SiLabs C2 2-wire interface | |
ETB Trace ARM7/9 | |
ETB Trace Cortex-M | |
ETB Trace Cortex-A/R | |
ETM Trace Cortex-M | |
VCOM | |
Memory Stop mode support | |
Cortex-M Monitor Mode debugging | |
SWD Multi-Drop | |
CMSIS-DAP mode |
Supported cores
J-Link provides debugging support for the following cores.
Note:
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
Core | Supported |
---|---|
ARM legacy Cores | |
ARM7 | |
ARM9 | |
ARM11 | |
ARM Cortex Cores | |
Cortex-A5 | |
Cortex-A7 | |
Cortex-A8 | |
Cortex-A9 | |
Cortex-A12 | |
Cortex-A15 | |
Cortex-A17 | |
Cortex-A53 | |
Cortex-A55 | |
Cortex-A57 | |
Cortex-A72 | |
Cortex-M0 | |
Cortex-M0+ | |
Cortex-M1 | |
Cortex-M3 | |
Cortex-M4 | |
Cortex-M7 | |
Cortex-M23 | |
Cortex-M33 | |
Cortex-R4 | |
Cortex-R5 | |
Cortex-R8 | |
SC000 (M0 secure) | |
SC300 (M3 secure) | |
RISC-V | |
RV32 | |
RV64 | |
Microchip PIC32 | |
PIC32MX | |
PIC32MZ | |
SiLabs 8051 | |
EFM8 | |
Renesas RX | |
RX110 | |
RX111 | |
RX210 | |
RX21A | |
RX220 | |
RX610 | |
RX621 | |
RX62G | |
RX62G | |
RX62N | |
RX62T | |
RX630 | |
RX631 | |
RX63N | |
RX63T | |
RX64M |