SemiDrive E31xx
Revision as of 15:13, 15 May 2024 by Simon Buchholz (talk | contribs)
Contents
The SemiDrive E31xx are Cortex-R5 based MCUs.
Internal Flash
E31xx devices consist of a SIP and have an internal QSPI flash.
Therefore programming the internal flash requires special handling. For more information about this, please see the QSPI Flash Programming Support article.
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Main flash | 0x10000000 | Up to 4 MB |
ECC RAM
E31xx devices have ECC RAM which can be disabled. However, a connect to E31xx devices will initialize 128KB at 0x500000 (1MB at 0x400000 for E3110).
Reset
No device specific reset is necessary. The normal Cortex-R reset is performed.
See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices