Renesas RZ/G2L SMARC EVK
Revision as of 13:20, 4 June 2021 by Matthias (talk | contribs) (Matthias moved page NXP RZG2L SWARC EVK to Renesas RZG2L SWARC EVK: Wrong page title)
This article describes specifics for the Renesas RZG2L EVK. A generic startup guide + additional information can be found on Renesas website.
Minimum requirements
- J-Link software V7.22 or later
Preparing for J-Link
- Connect the J-Link to the SWD header (CN2) on the SWARC module
- Power the board via CN6 (Power Input)
- Press the POWER button (SW9) in order to supply the SWARC module with power
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Renesas RZG2Lf. It is a simple Hello World sample linked into the internal RAM.
SETUP
- J-Link software: V7.22
- Embedded Studio: V5.42
- Hardware: Renesas RZG2L EVK (SWARC module)
- Link: File:Renesas RZG2L RAM TestProject ES V542.zip