Template:Renesas RA8
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support | Loaders |
---|---|---|---|---|
Code flash option-setting memory (secure) | 0x0300A100 | 384 B |
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Code flash option-setting memory (non-secure) | 0x1300A180 | 128 B |
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Data flash option-setting memory | 0x27030080 | 720 B |
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Code flash (secure) | 0x02000000 | Up to 2048 KB |
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Code flash (non-secure) | 0x12000000 | Up to 2048 KB |
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Data flash (secure) | 0x27000000 | Up to 12 KB |
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Data flash (non-secure) | 0x37000000 | Up to 12 KB |
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QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
Flash programming in OSPI mode is supported for Infineon S28HL512T and S28HS512T only. Other flashes are handled in single/quad mode.
Bank name | Base address | Maximum size | Supported pin configuration |
---|---|---|---|
External OSPI flash CS0 | 0x80000000 | 256 MB |
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External OSPI flash CS1 | 0x90000000 | 256 MB |
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Watchdog Handling
- The device has two watchdogs: Watchdog Timer (WDT) and Independent Watchdog Timer (IWDT).
- Both watchdogs are fed during flash programming.
Device Specific Handling
Connect
During connect the current security state of the device is determined. Depending on the state J-Link will use different RAM areas for operations that require RAM (flash programming, clock speed measurements):
- OEM_PL2: 0x22000000-0x2200FFFF
- OEM_PL1: 0x320D0000-0x320DFFFF
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Limitations
Using OEM_PL1 state with J-Flash
Since OEM_PL1 state requires the use of non-secure RAM (0x320D0000-0x320DFFFF), the user has to ensure that the J-Flash project is set up to use this RAM area instead of the secure RAM. By default J-Flash projects are created with secure RAM area (0x22000000-0x2200FFFF) selected.