i.MXRT1060
This article coverst the NXP i.MXRT1060 family devices. As for all i.MXRT10xx devices, JTAG is not active per default. Instead SWD can be used. To activate JTAG on this target device eFuses must be set. For more information see the corresponding target reference manual.
Contents
ROM Bootloader
The i.MXRT1060 devices feature a ROM Bootloader. This requires specific adjustments to the application image in order for the device to boot and operate correctly.
Detailed information on the flash image structure expected by the target device can be found in the corresponding target reference manual.
An example application for the MIMXRT1060-EVK which satisfies the can be found here:
NXP MIMXRT1060-EVK example project
Flash Programming
NXP's iMXRT106x family features a Cortex-M7 core without internal flash but with support for QSPI and HyperFlash through a so called FLEXSPI controller. NXP's official evaluation board, the MIMXRT1050 EVK is shipped with a 512Mbit Hyper Flash device by default. Alternatively, a QSPI flash can be mounted but several board modifications (removing the hyper flash, adding resistors, etc...) are required. As both flashes are accessed through the same memory mapped address space, either the HyperFlash or the QSPI flash RAMCode needs to be used for memory accesses to this area. Please find below further information how to select the desired flash loader. Official flash programming support has been added in J-Link software version V6.31d.
Resetting the device in the init steps may lead to problems when programming in standalone mode.
Requirements
- Min. J-Link software version V6.40 (release) is required. Later versions will also work. Earlier versions do not support flash programming on this device.
In order to be able to program a i.MXRT106x device, we expect that the first 0x10000 bytes of the RAM are configured to execute instructions from. The purpose of the RAM banks can be configured through the FlexRAM-controller. In case you have a different configuration of the RAM banks, which is not compatible with our assumption, please contact us.
Available flash loaders
iMXRT106x
J-Link comes with multiple selectable FLEXSPI flashloaders for i.MXRT106x devices. There are several options to select a different loader than the default one.
Loader name | Pin configuration | Notes |
---|---|---|
HyperFlash | FLEXSPIB_DATA03 = GPIO_SD_B1_00 FLEXSPIB_DATA02 = GPIO_SD_B1_01 FLEXSPIB_DATA01 = GPIO_SD_B1_02 FLEXSPIB_DATA00 = GPIO_SD_B1_03 FLEXSPIB_SCLK = GPIO_SD_B1_04 FLEXSPIA_DQS = GPIO_SD_B1_05 FLEXSPIA_SS0_B = GPIO_SD_B1_06 FLEXSPIA_SCLK = GPIO_SD_B1_07 FLEXSPIA_DATA00 = GPIO_SD_B1_08 FLEXSPIA_DATA01 = GPIO_SD_B1_09 FLEXSPIA_DATA02 = GPIO_SD_B1_10 FLEXSPIA_DATA03 = GPIO_SD_B1_11 |
Default loader for MIMXRT106A-ALEXA MIMXRT106ADVL6A MIMXRT106CDVL6A MIMXRT106FDVL6A MIMXRT106LDVL6A MIMXRT106SDVL6A |
QSPI | FLEXSPIB_DATA03 = GPIO_SD_B1_00 FLEXSPIB_DATA02 = GPIO_SD_B1_01 FLEXSPIB_DATA01 = GPIO_SD_B1_02 FLEXSPIB_DATA00 = GPIO_SD_B1_03 FLEXSPIB_SCLK = GPIO_SD_B1_04 FLEXSPIA_DQS = GPIO_SD_B1_05 FLEXSPIA_SS0_B = GPIO_SD_B1_06 FLEXSPIA_SCLK = GPIO_SD_B1_07 FLEXSPIA_DATA00 = GPIO_SD_B1_08 FLEXSPIA_DATA01 = GPIO_SD_B1_09 FLEXSPIA_DATA02 = GPIO_SD_B1_10 FLEXSPIA_DATA03 = GPIO_SD_B1_11 |
Default loader for MIMXRT1061xxx5A MIMXRT1061xxx5B MIMXRT1061xxx6A MIMXRT1061xxx6B MIMXRT1062xxx5A MIMXRT1062xxx5B MIMXRT1062xxx6A MIMXRT1062xxx6B MIMXRT106A-ALEXA2 |
Between V7.70d and V7.82c the default loader for MIMXRT1061xxx5A, MIMXRT1061xxx5B, MIMXRT1061xxx6A, MIMXRT1061xxx6B, MIMXRT1062xxx5A, MIMXRT1062xxx5B, MIMXRT1062xxx6A, MIMXRT1062xxx6B and MIMXRT106A-ALEXA2 was mistakenly set to HyperFlash. This issue has been fixed with V7.82d.
iMXRT1064
For iMXRT1064 currently only QSPI configuration is supported.
Loader name | Pin configuration | Notes |
---|---|---|
QSPI | FLEXSPIB_DATA03 = GPIO_SD_B1_00 FLEXSPIB_DATA02 = GPIO_SD_B1_01 FLEXSPIB_DATA01 = GPIO_SD_B1_02 FLEXSPIB_DATA00 = GPIO_SD_B1_03 FLEXSPIB_SCLK = GPIO_SD_B1_04 FLEXSPIA_DQS = GPIO_SD_B1_05 FLEXSPIA_SS0_B = GPIO_SD_B1_06 FLEXSPIA_SCLK = GPIO_SD_B1_07 FLEXSPIA_DATA00 = GPIO_SD_B1_08 FLEXSPIA_DATA01 = GPIO_SD_B1_09 FLEXSPIA_DATA02 = GPIO_SD_B1_10 FLEXSPIA_DATA03 = GPIO_SD_B1_11 |
Default loader |
Evaluation Boards
Tracing on NXP iMXRT106x
This section describes how to get started with trace on the NXP iMXRT106x MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).
- The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
- The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
- In order to rebuild the sample project, SEGGER Embedded Studio can be used.
The examples are shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
- To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing
Tracing on NXP iMXRT1064
Minimum requirements
In order to use trace on the NXP iMXRT1064 devices, the following minimum requirements have to be met:
- J-Link software version V7.94c or later
- Ozone V3.30d or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Streaming trace
The project below has been tested with the minimum requirements mentioned above and a VisionSOM-RT + VisionCB-RT-STD eval board.
- Example project: NXP_MIMXRT1064_TracePins.zip
Tested Hardware
The example project was tested with a VisionSOM-RT + VisionCB-RT-STD eval board. The pins used are:
- GPIO_B0_12 => TCLK
- GPIO_B0_04 => TD0
- GPIO_B0_05 => TD1
- GPIO_B0_06 => TD2
- GPIO_B0_07 => TD3
So if your own board is using the same pin combination the example project should work out of the box as well.