Difference between revisions of "ArteryTek AT-START-F421"
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| GND || J1 || 23 || GND |
| GND || J1 || 23 || GND |
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| − | | |
+ | | SWDIO || J1 || 10 || PA13 |
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| − | | |
+ | | SWCLK || J1 || 13 || PA14 |
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| RESET || J2 || 7 || NRST |
| RESET || J2 || 7 || NRST |
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Revision as of 18:57, 22 January 2024
This article describes specifics for the Artery AT-START-F421 evaluation board.
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Preparing for J-Link
- Connect the J-Link to this pins:
| J-Link Pin | Connector | Pin | Name |
|---|---|---|---|
| VTref | J1 | 24 | VDD |
| GND | J1 | 23 | GND |
| SWDIO | J1 | 10 | PA13 |
| SWCLK | J1 | 13 | PA14 |
| RESET | J2 | 7 | NRST |
- Power the board via USB (CN2 or CN3).
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Artery AT-START-F425.
It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.94g
- Embedded Studio: V7.20
- Hardware: Artery AT-START-F421
- Link: File:Artery AT-START-F425 AT32F425R8T7-7 TestProject ES 7V20.zip
