Difference between revisions of "ArteryTek AT32F42x"
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| − | + | ArteryTek AT32F42x are Cortex-M4 based MCUs |
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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| − | | Internal flash || 0x08000000 || Up to |
+ | | Internal flash || 0x08000000 || Up to 128 KB || style="text-align:center;"| {{YES}} |
| + | |- |
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| + | | User data || 0x1FFFF800 || 512 B || style="text-align:center;"| {{YES}} |
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==Device Specific Handling== |
==Device Specific Handling== |
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| + | ===Connect=== |
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| + | *On Connect, protection level is checked. For further information regarding this, please click [[ArteryTek_AT32| here]]. |
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| + | |||
===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *[[ |
+ | *[[ArteryTek_AT-START-F421|ArteryTek AT-START-F421]] |
| + | *[[ArteryTek_AT-START-F423|ArteryTek AT-START-F423]] |
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| − | |||
| + | *[[ArteryTek_AT-START-F425|ArteryTek AT-START-F425]] |
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==Example Application== |
==Example Application== |
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| − | *[[ |
+ | *[[ArteryTek_AT-START-F421#Example_Project | ArteryTek AT-START-F421]] |
| − | *[[ |
+ | *[[ArteryTek_AT-START-F423#Example_Project | ArteryTek AT-START-F423]] |
| + | *[[ArteryTek_AT-START-F425#Example_Project | ArteryTek AT-START-F425]] |
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Latest revision as of 12:01, 12 March 2024
ArteryTek AT32F42x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 128 KB | 
|
| User data | 0x1FFFF800 | 512 B |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
