Difference between revisions of "ArteryTek AT32F42x"
(Created page with "Artery AT32F43x are Cortex-M4 based MCUs __TOC__ ==Flash Banks== ===Internal Flash=== {| class="seggertable" |- ! Flash Bank || Base address !! Size || J-Link Support |- | In...") |
|||
| (9 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
| − | + | ArteryTek AT32F42x are Cortex-M4 based MCUs |
|
__TOC__ |
__TOC__ |
||
| Line 8: | Line 8: | ||
! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
||
|- |
|- |
||
| − | | Internal flash || 0x08000000 || Up to |
+ | | Internal flash || 0x08000000 || Up to 128 KB || style="text-align:center;"| {{YES}} |
| − | |} |
||
| − | |||
| − | ===QSPI Flash=== |
||
| − | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
||
| − | J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in '''bold'''. |
||
| − | {| class="seggertable" |
||
|- |
|- |
||
| + | | User data || 0x1FFFF800 || 512 B || style="text-align:center;"| {{YES}} |
||
| − | ! Device !! Base address !! Maximum size !! Supported pin configuration |
||
| − | |- |
||
| − | | '''QSPI1'''<br> |
||
| − | AT32F435<br> |
||
| − | AT32F437 |
||
| − | || 0x90000000 || Up to 64 MB || |
||
| − | *'''CLK@PF10 CS@PG6 IO0@PF9 IO1@PF8 IO2@PF7 IO3_@PF6''' |
||
|} |
|} |
||
| Line 29: | Line 17: | ||
==Device Specific Handling== |
==Device Specific Handling== |
||
| + | ===Connect=== |
||
| + | *On Connect, protection level is checked. For further information regarding this, please click [[ArteryTek_AT32| here]]. |
||
| + | |||
===Reset=== |
===Reset=== |
||
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
||
==Evaluation Boards== |
==Evaluation Boards== |
||
| − | *[[ |
+ | *[[ArteryTek_AT-START-F421|ArteryTek AT-START-F421]] |
| − | *[[ |
+ | *[[ArteryTek_AT-START-F423|ArteryTek AT-START-F423]] |
| + | *[[ArteryTek_AT-START-F425|ArteryTek AT-START-F425]] |
||
==Example Application== |
==Example Application== |
||
| − | *[[ |
+ | *[[ArteryTek_AT-START-F421#Example_Project | ArteryTek AT-START-F421]] |
| − | *[[ |
+ | *[[ArteryTek_AT-START-F423#Example_Project | ArteryTek AT-START-F423]] |
| + | *[[ArteryTek_AT-START-F425#Example_Project | ArteryTek AT-START-F425]] |
||
Latest revision as of 12:01, 12 March 2024
ArteryTek AT32F42x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 128 KB | 
|
| User data | 0x1FFFF800 | 512 B |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
