Difference between revisions of "Cyclone V series"

From SEGGER Wiki
Jump to: navigation, search
(Created page with "The Intel Cyclone V series FPGAs incorporate two hard-coded Cortex-A9 ARM cores. It is possible to debug both cores with J-Link (also explained later in this article)")
 
Line 1: Line 1:
  +
__TOC__
  +
 
The Intel Cyclone V series FPGAs incorporate two hard-coded Cortex-A9 ARM cores. It is possible to debug both cores with J-Link (also explained later in this article)
 
The Intel Cyclone V series FPGAs incorporate two hard-coded Cortex-A9 ARM cores. It is possible to debug both cores with J-Link (also explained later in this article)

Revision as of 17:40, 21 March 2017


The Intel Cyclone V series FPGAs incorporate two hard-coded Cortex-A9 ARM cores. It is possible to debug both cores with J-Link (also explained later in this article)