Difference between revisions of "Cyclone V series"
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| − | The Intel Cyclone V series FPGAs incorporate two hard-coded Cortex-A9 ARM cores. |
+ | The Intel Cyclone V series FPGAs incorporate two hard-coded Cortex-A9 ARM cores. |
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| + | == Multi-core debugging == |
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| + | J-Link supports debugging both Cortex-A9 cores of the Cyclone V. What is needed is one instance of the IDE (SEGGER Ozone, Eclipse + GDBServer, ...) per core to be debugged. |
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| + | === Connecting to core 0 === |
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| + | Connecting to core 0 (default core being available after startup of the device) does not require any special setup. All that needs to be done is selecting the correct device in the IDE, which is "'''Cyclone V'''", and start the debug session. |
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Revision as of 17:53, 21 March 2017
The Intel Cyclone V series FPGAs incorporate two hard-coded Cortex-A9 ARM cores.
Multi-core debugging
J-Link supports debugging both Cortex-A9 cores of the Cyclone V. What is needed is one instance of the IDE (SEGGER Ozone, Eclipse + GDBServer, ...) per core to be debugged.
Connecting to core 0
Connecting to core 0 (default core being available after startup of the device) does not require any special setup. All that needs to be done is selecting the correct device in the IDE, which is "Cyclone V", and start the debug session.
