DAP

The debug access port (DAP) means the DP and all APs that are connected to the DP. It is to describe the whole debug hierarchy. TBD

DP

The CoreSight debug port (DP) translates from the physical protocol that is used to communicate with the debug logic to the ARM specific internal debug logic. There are different types of DPs:

• JTAG-DP
• SW-DP
• SWJ-DP

JTAG-DP

JTAG is used to exchange information with the debug logic. The physical protocol may be 4-wire JTAG (IEEE 1149.1) or 2-wire cJTAG (IEEE 1149.7).

cJTAG and DP

Device internally, the DP understands 4-wire JTAG only. In case externally cJTAG is used as the physical protocol, there is a device internal 2-to-4-wire converter unit in front of the JTAG-DP that translates from cJTAG to JTAG. The DP still sees 4 signals internally, but only 2 are physically available at the pins of the MCU.

SW-DP

2-wire Serial Wire Debug (SWD) is used to exchange information with the debug logic.

SWJ-DP

JTAG or SWD may be used to exchange information with the debug logic. The protocol is switched between JTAG and SWD at runtime, using specific switching sequences that are specified by ARM and do not hurt JTAG devices that may be in the same JTAG chain as the SWJ-DP.

AP

A CoreSight access port (AP) mainly is a memory bus interface to access the actual debug logic / resources. While the DP performs the protocol translation, an AP usually performs real memory accesses to read/write debug register. There are different types of APs:

• AHB-AP
• APB-AP
• AXI-AP
• JTAG-AP

AHB-AP

TBD

APB-AP

TBD

AXI-AP

TBD

JTAG-AP

TBD

DAP topology Cortex-M

TBD

DAP topology Cortex-A

TBD

DAP topology Cortex-R

See Test