Difference between revisions of "GigaDevice GD32A5"
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| Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} |
| Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}} |
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|} |
|} |
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| + | |||
==ECC RAM== |
==ECC RAM== |
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| − | |||
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM |
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM |
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starting at 0x2000 0000. |
starting at 0x2000 0000. |
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| + | ==Watchdog Handling== |
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| − | ==Supported Flash Banks== |
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| + | *The device does have 2 watchdogs. |
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| − | ===Internal Flash=== |
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| + | *The watchdogs are fed during flash programming. |
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| − | {| class="seggertable" |
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| − | |- |
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| − | ! Device || StartAddr || Size || J-Link Support |
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| − | |- |
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| − | | GD32A503xB || 0x08000000 || 128Kb || scope="col" style="text-align:center" | {{YES}} |
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| − | |- |
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| − | | GD32A503xC || 0x08000000 || 256Kb || scope="col" style="text-align:center" | {{YES}} |
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| − | |- |
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| − | | GD32A503xD || 0x08000000 || 384Kb || scope="col" style="text-align:center" | {{YES}} |
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| − | |} |
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| − | |||
| − | ===Option Byte === |
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| − | {| class="seggertable" |
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| − | |- |
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| − | ! Device || StartAddr || Size || J-Link Support |
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| − | |- |
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| − | | GD32A503xx || 0x1FFFF800 || 24 Byte || scope="col" style="text-align:center" | {{YES}} |
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| − | |} |
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| + | ==Device Specific Handling== |
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| − | ==Reset== |
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| + | ===Connect=== |
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| − | The device uses normal reset, no special handling necessary. |
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| + | ===Reset=== |
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| − | ==Minimum requirements== |
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| + | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | * J-Link software V7.82b or later |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *GigaDevice GD32A503-EVAL |
+ | *[[GigaDevice_GD32A503-EVAL|GigaDevice GD32A503-EVAL]] |
==Example Application== |
==Example Application== |
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| + | *[[GigaDevice_GD32A503-EVAL#Example_Project | GigaDevice GD32A503-EVAL]] |
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| − | *GigaDevice GD32A503-EVAL evaluation board: https://wiki.segger.com/GigaDevice_GD32A503-EVAL#Example_Project |
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Revision as of 11:56, 15 February 2024
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M33 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash Bank 0 | 0x08000000 | Up to 256 KB | 
|
| Main flash Bank 1 | 0x08040000 | 128 KB |
|
| Option Byte 0 | 0x1FFFF800 | 24 B |
|
ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
