Difference between revisions of "GigaDevice GD32A5"
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The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® |
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® |
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| − | Cortex®-M33 processor. |
+ | Cortex®-M33 processor. |
| + | __TOC__ |
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| − | ==Internal RAM== |
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| + | |||
| − | 24/36/48 Kb ECC |
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| − | == |
+ | ==Flash Banks== |
| + | ===Internal Flash=== |
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| − | 128/256/384 Kb |
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| + | {| class="seggertable" |
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| − | ==QSPI Flash== |
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| + | |- |
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| − | n/a |
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| + | ! Flash Bank || Base address !! Size || J-Link Support |
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| − | ===Supported Regions=== |
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| + | |- |
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| − | Internal Flash 0x0800 0000 - 0x0801 FFFF <br> |
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| + | | Main flash Bank 0 || 0x08000000 || Up to 256 KB || style="text-align:center;"| {{YES}} |
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| − | Internal Flash 0x0800 0002 - 0x0803 FFFF <br> |
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| + | |- |
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| − | Internal Flash 0x0800 0004 - 0x0805 FFFF <br> |
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| + | | Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} |
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| − | ==Reset== |
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| + | |- |
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| − | The device uses normal reset, no special handling necessary. |
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| + | | Data flash || 0x08800000 || up to 64 KB || style="text-align:center;"| {{NO}} |
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| − | ===ECC RAM=== |
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| + | |- |
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| − | In order to prevent errors when reading first time, the DLL intialises the first 24Kb of RAM |
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| + | | Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | Option Byte 1 || 0x4002 2068|| 4 B || style="text-align:center;"| {{NO}} |
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| + | |- |
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| + | | OTP Bytes || 0x1FFF7000 || 1 KB || style="text-align:center;"| {{NO}} |
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| + | |} |
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| + | |||
| + | ==ECC RAM== |
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| + | In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM |
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starting at 0x2000 0000. |
starting at 0x2000 0000. |
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| + | |||
| + | ==Watchdog Handling== |
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| + | *The device does have 2 watchdogs. |
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| + | *The watchdogs are fed during flash programming. |
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| + | |||
| + | ==Device Specific Handling== |
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| + | ===Connect=== |
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| + | * On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]]. |
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| + | |||
| + | ===Reset=== |
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| + | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| + | |||
==Evaluation Boards== |
==Evaluation Boards== |
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| + | *[[GigaDevice_GD32A503-EVAL|GigaDevice GD32A503-EVAL]] |
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| − | *#### evaluation board: https://wiki.segger.com/#### |
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==Example Application== |
==Example Application== |
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| + | *[[GigaDevice_GD32A503-EVAL#Example_Project | GigaDevice GD32A503-EVAL]] |
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| − | *##### evaluation board: https://wiki.segger.com/######Example_Project |
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Latest revision as of 16:27, 16 February 2024
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M33 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash Bank 0 | 0x08000000 | Up to 256 KB | 
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| Main flash Bank 1 | 0x08040000 | 128 KB |
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| Data flash | 0x08800000 | up to 64 KB | 
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| Option Byte 0 | 0x1FFFF800 | 24 B |
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| Option Byte 1 | 0x4002 2068 | 4 B |
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| OTP Bytes | 0x1FFF7000 | 1 KB |
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ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
