Difference between revisions of "GigaDevice GD32A5"
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| Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} |
| Main flash Bank 1 || 0x08040000 || 128 KB || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | Data flash || 0x08800000 || up to 64 KB || style="text-align:center;"| {{NO}} |
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| Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}} |
| Option Byte 0 || 0x1FFFF800 || 24 B || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | Option Byte 1 || 0x4002 2068|| 4 B || style="text-align:center;"| {{NO}} |
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| + | |- |
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| + | | OTP Bytes || 0x1FFF7000 || 1 KB || style="text-align:center;"| {{NO}} |
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==ECC RAM== |
==ECC RAM== |
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==Device Specific Handling== |
==Device Specific Handling== |
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===Connect=== |
===Connect=== |
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| + | * On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]]. |
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===Reset=== |
===Reset=== |
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Latest revision as of 16:27, 16 February 2024
The GD32A50x series are 32-bit general-purpose microcontrollers based on the Arm® Cortex®-M33 processor.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash Bank 0 | 0x08000000 | Up to 256 KB | 
|
| Main flash Bank 1 | 0x08040000 | 128 KB |
|
| Data flash | 0x08800000 | up to 64 KB | 
|
| Option Byte 0 | 0x1FFFF800 | 24 B |
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| Option Byte 1 | 0x4002 2068 | 4 B |
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| OTP Bytes | 0x1FFF7000 | 1 KB |
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ECC RAM
In order to prevent errors when reading first time, the DLL initializes the first 24Kb of RAM starting at 0x2000 0000.
Watchdog Handling
- The device does have 2 watchdogs.
- The watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
