Difference between revisions of "GigaDevice GD32F3"

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*[[GigaDevice_GD32303E-EVAL | GigaDevice GD32303E-EVAL]]
 
*[[GigaDevice_GD32303E-EVAL | GigaDevice GD32303E-EVAL]]
 
*[[GigaDevice_GD32305R-START | GigaDevice GD32305R-START]]
 
*[[GigaDevice_GD32305R-START | GigaDevice GD32305R-START]]
*[[GigaDevice_GD32307C-EVAL | GigaDevice GD32307C-EVAL]]
 
 
*[[GigaDevice_GD32307C-EVAL | GigaDevice GD32307C-EVAL]]
 
*[[GigaDevice_GD32307C-EVAL | GigaDevice GD32307C-EVAL]]
 
*[[GigaDevice_GD32330C-START | GigaDevice GD32330C-START]]
 
*[[GigaDevice_GD32330C-START | GigaDevice GD32330C-START]]
*[[GigaDevice_GD32330C-START | GigaDevice GD32330C-START]]
 
*[[GigaDevice_GD32350C-START | GigaDevice GD32350C-START]]
 
 
*[[GigaDevice_GD32350C-START | GigaDevice GD32350C-START]]
 
*[[GigaDevice_GD32350C-START | GigaDevice GD32350C-START]]
 
*[[GigaDevice_GD32350R-EVAL | GigaDevice GD32350R-EVAL]]
 
*[[GigaDevice_GD32350R-EVAL | GigaDevice GD32350R-EVAL]]
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*[[GigaDevice_GD32305R-START#Example_Project | GigaDevice GD32305R-START]]
 
*[[GigaDevice_GD32305R-START#Example_Project | GigaDevice GD32305R-START]]
 
*[[GigaDevice_GD32307C-EVAL#Example_Project | GigaDevice GD32307C-EVAL]]
 
*[[GigaDevice_GD32307C-EVAL#Example_Project | GigaDevice GD32307C-EVAL]]
*[[GigaDevice_GD32307C-EVAL#Example_Project | GigaDevice GD32307C-EVAL]]
 
*[[GigaDevice_GD32330C-START#Example_Project | GigaDevice GD32330C-START]]
 
 
*[[GigaDevice_GD32330C-START#Example_Project | GigaDevice GD32330C-START]]
 
*[[GigaDevice_GD32330C-START#Example_Project | GigaDevice GD32330C-START]]
*[[GigaDevice_GD32350C-START#Example_Project | GigaDevice GD32350C-START]]
 
 
*[[GigaDevice_GD32350C-START#Example_Project | GigaDevice GD32350C-START]]
 
*[[GigaDevice_GD32350C-START#Example_Project | GigaDevice GD32350C-START]]
 
*[[GigaDevice_GD32350R-EVAL#Example_Project | GigaDevice GD32350R-EVAL]]
 
*[[GigaDevice_GD32350R-EVAL#Example_Project | GigaDevice GD32350R-EVAL]]

Latest revision as of 11:32, 27 February 2024

The GigaDevice GD32F3 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
Main flash 0x08000000 Up to 256 KB YES.png
Option Bytes 0x1FFFF800 16 B YES.png

Watchdog Handling

  • The device does have 2 watchdogs, FWDGT and WWDGT.
  • The WWDGT watchdog is fed during flash programming.

Device Specific Handling

Connect

  • On Connect, protection level is checked. For further information regarding this, please click here.

Reset

  • The device uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

Example Application