Difference between revisions of "GigaDevice GD32H7"
Arne.kulinna (talk | contribs) (Created page with "__TOC__ The GigaDevice GD32H7 are Cortex-M7 based MCUs. ==Internal Flash== {| class="seggertable" |- ! Flash Bank || Base address !! Size || J-Link Support |- | Main flash ||...") |
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GD32H7 devices have ECC RAM which can be disabled. However, a connect to GD32H7 devices will initialize 16KB at 0x20000000. |
GD32H7 devices have ECC RAM which can be disabled. However, a connect to GD32H7 devices will initialize 16KB at 0x20000000. |
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| − | For more information, refer to the [[ECC | ECC article |
+ | For more information, refer to the [[ECC | ECC article]]. |
==Reset== |
==Reset== |
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No device specific reset is necessary. The normal Cortex-M reset is performed. |
No device specific reset is necessary. The normal Cortex-M reset is performed. |
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| − | See here for more information: |
+ | See here for more information: [[J-Link_Reset_Strategies#Type_0:_Normal | J-Link Reset Strategies]] |
==Evaluation Boards== |
==Evaluation Boards== |
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| + | * [[GigaDevice_GD32H759I-EVAL | GigaDevice GD32H759I-EVAL]] |
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| − | *GigaDevice GD32H759I-EVAL: https://wiki.segger.com/GigaDevice_GD32H759I-EVAL |
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Latest revision as of 09:42, 2 November 2023
The GigaDevice GD32H7 are Cortex-M7 based MCUs.
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x08000000 | Up to 3840 KB | 
|
Internal ECC RAM
GD32H7 devices have ECC RAM which can be disabled. However, a connect to GD32H7 devices will initialize 16KB at 0x20000000. For more information, refer to the ECC article.
Reset
No device specific reset is necessary. The normal Cortex-M reset is performed.
See here for more information: J-Link Reset Strategies
