Difference between revisions of "Infineon TLE987x"
(Created page with "__TOC__ The Infineon TLE987x series devices Xilinx ZedBoard is a complete development kit for the Xilinx Zynq7000 SoC. The Xilinx Zynq7000 is a high-end SoC which incorporate...") |
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| + | The Infineon TLE987x series is a 3-phase bridge driver IC, incorporating an ARM Cortex-M3 core. |
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| − | The Infineon TLE987x series devices Xilinx ZedBoard is a complete development kit for the Xilinx Zynq7000 SoC. The Xilinx Zynq7000 is a high-end SoC which incorporates a dual core Cortex-A9 (2x Cortex-A9) and programmable FPGA logic on-chip. |
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= J-Link support = |
= J-Link support = |
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| − | J-Link supports the |
+ | J-Link supports the Infineon TLE987x series devices. [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack Download latest release] |
| − | + | = J-Link device selection in IDE = |
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| + | The device selection is mandatory to make sure that J-Link applies the correct connect and reset sequences to the TLE 987x series devices. By selecting "generic Cortex-M3" correct functionality cannot be guaranteed. This is mainly because the TLE987x series need a special connect sequence that makes sure that TCK/SWCLK and TMS/SWDIO are sampled with the correct values after reset, to enable the debug interface (JTAG/SWD). |
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| − | Please note that for the device selection in J-Link Commander, quotes are needed around the device name (as shown in the screenshot below). This is due to the nature of the Zynq7000 device names, containing spaces. Apart from that, there is nothing special to be taken care of. |
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| + | = Device readout protection = |
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| − | '''Note:''' The device selection is mandatory to make sure that J-Link applies the correct connect and reset sequences to the Zynq 7000 series devices. By selecting "generic Cortex-A9" correct functionality cannot be guaranteed. |
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| + | Once the readout protection of the device has been activated, it cannot be unprotected via the debug interface (JTAG/SWD) anymore. J-Link can still access the debug registers but not more. It is no longer possible to access any other memory through the debug interface or to issue halt requests etc. to the core (they will be ignored) |
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| − | [[File:Xilinx_Zynq7020_ZedBoard_Commander.png|Xilinx ZedBoard|thumb|none]] |
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| − | = |
+ | = Low power modes = |
| + | It is recommended to not enter low power modes during debug because this will lead to a connection loss. It is also recommended to wait at least 20ms after reset release before entering a low power mode. Otherwise J-Link may be unable to gain control over a already programmed device that is running a software that enters low power modes (which effectively disables debug access) |
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| − | The ZedBoard provides a Xilinx specific 14-pin debug connector. In order to connect J-Link to this board, the [https://www.segger.com/products/debug-probes/j-link/accessories/adapters/xilinx-adapter/ J-Link Xilinx adapter] is needed. |
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| + | = Reset pin = |
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| − | [[File:Xilinx_ZedBoard_JTAGConnector.png|Debug header|thumb|none]] |
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| + | It is mandatory to connect the reset pin of the device to the J-Link debug connector. J-Link needs to be able to control the reset pin. Otherwise a proper connection to the device cannot be guaranteed. |
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| − | [[File:Xilinx_ZedBoard.png|Xilinx ZedBoard|thumb|none]] |
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| + | |||
| + | = Reset strategies = |
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| + | J-Link will always perform a reset of the core + peripherals via the AIRCR register and the reset pin. All other reset strategies that may be selectable in the IDE are ignored and will result in this reset strategy. |
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Revision as of 17:23, 2 October 2018
Contents
The Infineon TLE987x series is a 3-phase bridge driver IC, incorporating an ARM Cortex-M3 core.
J-Link support
J-Link supports the Infineon TLE987x series devices. Download latest release
J-Link device selection in IDE
The device selection is mandatory to make sure that J-Link applies the correct connect and reset sequences to the TLE 987x series devices. By selecting "generic Cortex-M3" correct functionality cannot be guaranteed. This is mainly because the TLE987x series need a special connect sequence that makes sure that TCK/SWCLK and TMS/SWDIO are sampled with the correct values after reset, to enable the debug interface (JTAG/SWD).
Device readout protection
Once the readout protection of the device has been activated, it cannot be unprotected via the debug interface (JTAG/SWD) anymore. J-Link can still access the debug registers but not more. It is no longer possible to access any other memory through the debug interface or to issue halt requests etc. to the core (they will be ignored)
Low power modes
It is recommended to not enter low power modes during debug because this will lead to a connection loss. It is also recommended to wait at least 20ms after reset release before entering a low power mode. Otherwise J-Link may be unable to gain control over a already programmed device that is running a software that enters low power modes (which effectively disables debug access)
Reset pin
It is mandatory to connect the reset pin of the device to the J-Link debug connector. J-Link needs to be able to control the reset pin. Otherwise a proper connection to the device cannot be guaranteed.
Reset strategies
J-Link will always perform a reset of the core + peripherals via the AIRCR register and the reset pin. All other reset strategies that may be selectable in the IDE are ignored and will result in this reset strategy.
