Difference between revisions of "J-Link zoned memory access"
(→ARM Cortex-A/R/M specific memory zones) |
|||
| Line 13: | Line 13: | ||
* APB-AP to have a 32-bit address space to place debug registers of the core into and so isolate them from the application/core, so they cannot access them by accident. |
* APB-AP to have a 32-bit address space to place debug registers of the core into and so isolate them from the application/core, so they cannot access them by accident. |
||
* AHB-AP / AXI-AP to have a DMA-like access to system memory (flash, RAM, peripheral registers, ...) without involving the MPU / MMU / core. Allows for example background memory accesses to RAM without halting the core and so making use of features like [[HSS | SEGGER HSS]] and [[RTT | SEGGER RTT]]. |
* AHB-AP / AXI-AP to have a DMA-like access to system memory (flash, RAM, peripheral registers, ...) without involving the MPU / MMU / core. Allows for example background memory accesses to RAM without halting the core and so making use of features like [[HSS | SEGGER HSS]] and [[RTT | SEGGER RTT]]. |
||
| + | * AXI-AP to have a DMA-like access to system memory (flash, RAM, peripheral registers, ...) without involving the MPU / MMU / core. Allows for example background memory accesses to RAM without halting the core and so making use of features like [[HSS | SEGGER HSS]] and [[RTT | SEGGER RTT]]. |
||
== SiLabs EFM8 specific memory zones == |
== SiLabs EFM8 specific memory zones == |
||
Revision as of 09:45, 20 March 2023
In many MCUs, there are different memory views available via a debugger / debug probe. Some examples are:
- Core view (same view as the CPU / core has)
- Uncached view
- Cached view
- ...
Contents
ARM Cortex-A/R/M specific memory zones
On ARM Cortex-A/R/M based MCUs, besides the "core view" there are also so-called MEM-AP views available.
A MEM-AP is a DMA-like piece of hardware but with its own 32-bit (4 GiB) address space (AXI-APs have 48-bit).
MEM-APs are used for various purposes:
- APB-AP to have a 32-bit address space to place debug registers of the core into and so isolate them from the application/core, so they cannot access them by accident.
- AHB-AP / AXI-AP to have a DMA-like access to system memory (flash, RAM, peripheral registers, ...) without involving the MPU / MMU / core. Allows for example background memory accesses to RAM without halting the core and so making use of features like SEGGER HSS and SEGGER RTT.
- AXI-AP to have a DMA-like access to system memory (flash, RAM, peripheral registers, ...) without involving the MPU / MMU / core. Allows for example background memory accesses to RAM without halting the core and so making use of features like SEGGER HSS and SEGGER RTT.
SiLabs EFM8 specific memory zones
TBD
Accessing memory zones
J-Link Commander
When connecting to a device, J-Link Commander will print the available zones, if any besides "default" are available:
...
Memory zones:
Zone: "Default" Description: Default access mode
Zone: "AP0" Description: MEM-AP (APB-AP)
Zone: "AP1" Description: MEM-AP (APB-AP)
Zone: "AP2" Description: MEM-AP (AXI-AP)
Cortex-R52 identified.
J-Link>The zones can be used by the memory commands:
- mem / mem32 / ...
- w1 / w2 / w4 / w8
Taking the example from above, issuing a 64-bit item write to address 0x2000_0000 via the AXI-AP, the following command may be used:
w8 AP2:0x20000000 0x1122334455667788To read 256 (0x100) bytes @ 0x2000_0000 via the AXI-AP, the following command may be used:
mem AP2:0x20000000, 100Omitting the zone part accesses the "default" zone.
Ozone
TBD
