Difference between revisions of "Kinetis KE1xZ 48 MHz series"
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− | The NXP Kinetis KE1xZ 48 MHz series is |
+ | The NXP Kinetis KE1xZ 48 MHz series is designed for white goods and industrial applications. It incorporates an ARM Cortex-M0+ core. |
= J-Link support = |
= J-Link support = |
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− | The KE14Z32, KE14Z64, KE15Z32, KE15Z64, KE16Z32, KE16Z64 are supported |
+ | The KE14Z32, KE14Z64, KE15Z32, KE15Z64, KE16Z32, KE16Z64 are supported since the following J-Link software versions: |
+ | * V6.35g (beta) or later: [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPackBeta Download latest beta] |
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+ | * V6.36 (release) or later: [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack Download latest release] |
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+ | = Watchdog support = |
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− | [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPackBeta Download latest version] |
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+ | Debugging and flash programming with the watchdog (WDOG) being enabled (in non-windowed mode) is supported. Windowed mode of the watchdog is not supported for debugging and flash programming. |
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− | = |
+ | = MTB trace = |
+ | The KE1xZ 48 MHz series devices incorporate an ARM MTB on-chip trace buffer that allows instruction backtrace. For more information about MTB in general, please refer to here: [[MTB specifics | Article MTB]]. |
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− | The cores are named as follows: |
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− | |||
− | {| class="wikitable" |
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− | !Core name |
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− | !Description |
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− | |- |
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− | |Cortex-M33 (core 0) |
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− | |Main core that device boots from by default |
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− | |- |
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− | |Cortex-M33 (core 1) |
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− | |Secondary core that is not booted by default on reset release |
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− | |} |
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− | == J-Link device selection == |
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− | The following device names are available for J-Link: |
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− | |||
− | {| class="wikitable" |
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− | !Device name |
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− | !Function |
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− | |- |
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− | |SSE-200-MPS3 |
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− | |Connects to core 0 |
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− | |- |
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− | |SSE-200-MPS3_M33_0 |
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− | |Connects to core 0 |
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− | |- |
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− | |SSE-200-MPS3_M33_1 |
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− | |Connects to core 1. Core 1 is enabled (released from reset) automatically by J-Link, if necessary |
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− | |} |
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= Example projects = |
= Example projects = |
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+ | [https://wiki.segger.com/Tracing_on_NXP_Kinetis_KE1xZ MTB Trace] |
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− | There are sample projects available that demonstrate how to use J-Link with the ARM CoreLink SSE-200 prototyping platform. |
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− | |||
− | == SEGGER Embedded Studio (multi-core) == |
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− | The sample project for SEGGER Embedded Studio is a RAM based project and also demonstrates multi-core debugging. |
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− | The sample is actually split into 2 projects: |
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− | * [[Media:ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES.zip | ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES.zip]] |
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− | * [[Media:ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES.zip | ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES.zip]] |
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− | ''' ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES ''' |
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− | Loaded into internal SRAM and executed by core 0. Controls LED1 and LED2 on the MPS3 board. LED1 is always toggled, LED2 is toggled as long as core 1 is running its application and sending commands to core 0 |
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− | ''' ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES ''' |
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− | Loaded into internal SRAM and executed by core 1. Sends commands to core 0 that instruct the main application to toggle LED2 |
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− | === Usage === |
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− | * Start SEGGER Embedded Studio twice |
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− | * Open ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES and ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES accordingly |
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− | * Start debug session with project for core 0 |
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− | * Let CPU run as soon as main() has hit |
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− | * Start debug session with project for core 1 |
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− | * Let CPU run as soon as main() has hit |
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− | * LED1 and LED2 will blink |
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− | * Now halt core 1 (issue halt request in debug session for core 1) |
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− | * LED2 stops blinking, LED1 continues to blink |
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=== Requirements === |
=== Requirements === |
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The following are the min. requirements to run the example project: |
The following are the min. requirements to run the example project: |
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− | * SEGGER Embedded Studio V3. |
+ | * SEGGER Embedded Studio V3.52 or later |
− | * J-Link software V6. |
+ | * J-Link software V6.36 or later. (Install after Embedded Studio and let J-Link installer update the Embedded Studio installation) |
+ | * Board: [https://wiki.segger.com/FRDM-KE16Z FRDM-KE16Z] |
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− | * [[MPS3 | ARM MPS3 board]] |
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<references/> |
<references/> |
Latest revision as of 15:29, 18 October 2018
The NXP Kinetis KE1xZ 48 MHz series is designed for white goods and industrial applications. It incorporates an ARM Cortex-M0+ core.
J-Link support
The KE14Z32, KE14Z64, KE15Z32, KE15Z64, KE16Z32, KE16Z64 are supported since the following J-Link software versions:
- V6.35g (beta) or later: Download latest beta
- V6.36 (release) or later: Download latest release
Watchdog support
Debugging and flash programming with the watchdog (WDOG) being enabled (in non-windowed mode) is supported. Windowed mode of the watchdog is not supported for debugging and flash programming.
MTB trace
The KE1xZ 48 MHz series devices incorporate an ARM MTB on-chip trace buffer that allows instruction backtrace. For more information about MTB in general, please refer to here: Article MTB.
Example projects
Requirements
The following are the min. requirements to run the example project:
- SEGGER Embedded Studio V3.52 or later
- J-Link software V6.36 or later. (Install after Embedded Studio and let J-Link installer update the Embedded Studio installation)
- Board: FRDM-KE16Z