Difference between revisions of "MT7697 series"
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= J-Link support = |
= J-Link support = |
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| − | J-Link supports the |
+ | J-Link supports the MediatTek 7697 series since the following J-Link software versions: |
| − | * V6. |
+ | * V6.35a and later ([https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack Download latest version]) |
| − | * V6.34 (release) or later ([https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack Download latest release]) |
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| − | = |
+ | = Reset = |
| + | Unfortunately, on the MediaTek 7697 series the standard Cortex-M software triggered reset via AIRCR.SYSRESETREQ does not work (bit has no effect). |
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| − | The cores are named as follows: |
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| + | A reset via the reset pin cannot be used because it also resets the debug logic (e.g. vector catch etc. bits) which makes it impossible to halt the core immediately after reset, before it executes any instruction. |
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| − | {| class="wikitable" |
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| − | !Core name |
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| − | !Description |
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| − | |- |
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| − | |Cortex-M33 (core 0) |
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| − | |Main core that device boots from by default |
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| − | |- |
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| − | |Cortex-M33 (core 1) |
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| − | |Secondary core that is not booted by default on reset release |
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| − | |} |
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| + | For this device series, J-Link will issue a reset of the Cortex-M4 core only (AIRCR.VECTRESET). No peripherals etc. are reset by this reset. The Cortex-M4 core is halted after the secondary bootloader has run and jumped to the firmware image at 0x10079000 in QSPI flash. It is halted before any instruction of the firmware image is executed. |
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| − | == J-Link device selection == |
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| − | The following device names are available for J-Link: |
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| − | |||
| − | {| class="wikitable" |
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| − | !Device name |
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| − | !Function |
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| − | |- |
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| − | |SSE-200-MPS3 |
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| − | |Connects to core 0 |
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| − | |- |
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| − | |SSE-200-MPS3_M33_0 |
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| − | |Connects to core 0 |
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| − | |- |
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| − | |SSE-200-MPS3_M33_1 |
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| − | |Connects to core 1. Core 1 is enabled (released from reset) automatically by J-Link, if necessary |
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| − | |} |
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| − | |||
| − | = Example projects = |
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| − | There are sample projects available that demonstrate how to use J-Link with the ARM CoreLink SSE-200 prototyping platform. |
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| − | |||
| − | == SEGGER Embedded Studio (multi-core) == |
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| − | The sample project for SEGGER Embedded Studio is a RAM based project and also demonstrates multi-core debugging. |
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| − | The sample is actually split into 2 projects: |
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| − | * [[Media:ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES.zip | ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES.zip]] |
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| − | * [[Media:ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES.zip | ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES.zip]] |
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| − | |||
| − | ''' ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES ''' |
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| − | |||
| − | Loaded into internal SRAM and executed by core 0. Controls LED1 and LED2 on the MPS3 board. LED1 is always toggled, LED2 is toggled as long as core 1 is running its application and sending commands to core 0 |
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| − | |||
| − | ''' ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES ''' |
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| − | |||
| − | Loaded into internal SRAM and executed by core 1. Sends commands to core 0 that instruct the main application to toggle LED2 |
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| − | |||
| − | === Usage === |
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| − | * Start SEGGER Embedded Studio twice |
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| − | * Open ARM_SSE-200-MPS3_MPS3_LEDBlinkCore0_ES and ARM_SSE-200-MPS3_MPS3_LEDBlinkCore1_ES accordingly |
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| − | * Start debug session with project for core 0 |
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| − | * Let CPU run as soon as main() has hit |
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| − | * Start debug session with project for core 1 |
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| − | * Let CPU run as soon as main() has hit |
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| − | * LED1 and LED2 will blink |
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| − | * Now halt core 1 (issue halt request in debug session for core 1) |
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| − | * LED2 stops blinking, LED1 continues to blink |
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| − | |||
| − | === Requirements === |
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| − | The following are the min. requirements to run the example project: |
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| − | * SEGGER Embedded Studio V3.40 or later |
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| − | * J-Link software V6.33h or later. (Install after Embedded Studio and let J-Link installer update the Embedded Studio installation) |
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| − | * [[MPS3 | ARM MPS3 board]] |
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<references/> |
<references/> |
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Revision as of 15:46, 21 August 2018
Contents
The ARM CoreLink SSE-200 is a prototyping platform from ARM that allows prototyping of Cortex-M33 based devices on the ARM MPS3 board. It incorporates a dual-core Cortex-M33, lots of internal RAM (> 2 MB) and QSPI flash.
J-Link support
J-Link supports the MediatTek 7697 series since the following J-Link software versions:
- V6.35a and later (Download latest version)
Reset
Unfortunately, on the MediaTek 7697 series the standard Cortex-M software triggered reset via AIRCR.SYSRESETREQ does not work (bit has no effect).
A reset via the reset pin cannot be used because it also resets the debug logic (e.g. vector catch etc. bits) which makes it impossible to halt the core immediately after reset, before it executes any instruction.
For this device series, J-Link will issue a reset of the Cortex-M4 core only (AIRCR.VECTRESET). No peripherals etc. are reset by this reset. The Cortex-M4 core is halted after the secondary bootloader has run and jumped to the firmware image at 0x10079000 in QSPI flash. It is halted before any instruction of the firmware image is executed.
