Difference between revisions of "NXP Kinetis KE1xZ512"
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==Device Specific Handling== |
==Device Specific Handling== |
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| − | ===Connect=== |
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===Reset=== |
===Reset=== |
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*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| + | *[[NXP_FRDM-KE17Z512 | NXP FRDM-KE17Z512]] |
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| − | *[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]] |
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==Example Application== |
==Example Application== |
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| − | *[[ |
+ | *[[NXP_FRDM-KE17Z512#Example_Project | NXP FRDM-KE17Z512]] |
Revision as of 14:07, 6 November 2023
The NXP Kinetis KE1xZ512 are ARM® Cortex®-M0+ MCUs,
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00000000 | 512 KB | 
|
Watchdog Handling
- The device has a watchdog WDOG.
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
