Difference between revisions of "NXP MCXA10"
Line 13: | Line 13: | ||
====ECC Flash ==== |
====ECC Flash ==== |
||
*Device has ECC Flash, but no special handling required. |
*Device has ECC Flash, but no special handling required. |
||
− | |||
− | ==ECC RAM == |
||
− | *Device has 8KB ECC RAM named SRAM A0, can be used when LPCAC is switched off |
||
==Watchdog Handling== |
==Watchdog Handling== |
Latest revision as of 10:59, 13 March 2024
The NXP MCXA10 are single core ARM Cortex-M33 microprocessors.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal Flash | 0x00000000 | up to 128 KB |
ECC Flash
- Device has ECC Flash, but no special handling required.
Watchdog Handling
- The device has 2 watchdogs WWDT and CDOG.
- The watchdog WWDT is fed during flash programming.
- No handling for CDOG implemented.
Device Specific Handling
Reset
- The J-Link performs a device specific reset sequence. SRAM and Flash is set to RWX.
Attach
Attach is supported.
Evaluation Boards
NXP MCX-A14X-EVK evaluation board