Difference between revisions of "NXP MCXA18"
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====ECC Flash ==== |
====ECC Flash ==== |
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*Device has ECC Flash, but no special handling required. |
*Device has ECC Flash, but no special handling required. |
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| − | ==ECC RAM == |
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| − | *Device has 8KB ECC RAM named SRAM A0, can be used when LPCAC is switched off |
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==Watchdog Handling== |
==Watchdog Handling== |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | [[ |
+ | [[NXP_FRDM-MCXA156|NXP FRDM-MCXA156 evaluation board]] |
==Example Application== |
==Example Application== |
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| − | [[ |
+ | [[NXP_FRDM-MCXA156#Example_Project|NXP FRDM-MCXA156 evaluation board]] |
Latest revision as of 10:57, 13 March 2024
The NXP MCXA18 are single core ARM Cortex-M33 microprocessors.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash | 0x00000000 | up to 1024 KB | 
|
ECC Flash
- Device has ECC Flash, but no special handling required.
Watchdog Handling
- The device has 2 watchdogs WWDT and CDOG.
- The watchdog WWDT is fed during flash programming.
- No handling for CDOG implemented.
Device Specific Handling
Reset
- The J-Link performs a device specific reset sequence. SRAM and Flash is set to RWX.
Attach
Attach is supported.
Evaluation Boards
NXP FRDM-MCXA156 evaluation board
