Difference between revisions of "NXP NCJ29D5"
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+ | The '''NXP NCJ29D5''' are Ultra-Wideband (UWB) ICs designed specifically to meet the connectivity and safety needs of the global automotive industry. |
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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+ | | Normal-Domain Application || 0x00200000 || 128 KB || style="text-align:center;"| {{YES}} |
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+ | | RX Radio Configurations || 0x00238A000 || 8 KB || style="text-align:center;"| {{NO}} |
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+ | | TX Radio Configurations || 0x0023AA000 || 8 KB || style="text-align:center;"| {{NO}} |
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+ | | Customer Configuration Page || 0x0023C000 || 512 B || style="text-align:center;"| {{NO}} |
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+ | | Baseband DSP Firmware || 0x00230000 ||35 KB || style="text-align:center;"| {{NO}} |
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Revision as of 12:33, 10 May 2023
The NXP NCJ29D5 are Ultra-Wideband (UWB) ICs designed specifically to meet the connectivity and safety needs of the global automotive industry.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Normal-Domain Application | 0x00200000 | 128 KB | |
RX Radio Configurations | 0x00238A000 | 8 KB | |
TX Radio Configurations | 0x0023AA000 | 8 KB | |
Customer Configuration Page | 0x0023C000 | 512 B | |
Baseband DSP Firmware | 0x00230000 | 35 KB |
ECC Flash [OPTIONAL]
- Describe ECC Flash restriction here.
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in bold.
Device | Base address | Maximum size | Supported pin configuration |
---|---|---|---|
[DEVICE] | [BANK_BASE_ADDRESS] | [MAX_SPI_FLASH_SIZE] MB |
|
ECC RAM [OPTIONAL]
- Describe ECC RAM restriction here.
Vector Table Remap [OPTIONAL]
- Describe Vector Table Remap here..
Watchdog Handling
- The device does not have a watchdog.
- The device has a watchdog [WATCHDOGNAME].
- The watchdog is fed during flash programming.
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
- The devices uses Cortex-M Core reset, no special handling necessary, like described here.
- The devices uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project