Difference between revisions of "NXP i.MX 8"
m (Artjom.Kister moved page i.MX 8 to NXP i.MX 8) |
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+ | The '''NXP i.MX 8''' are embedded multi-core processors consisting of two Cortex-M4, four Cortex-A53 and two Cortex-A72. |
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− | == Debugging == |
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+ | __TOC__ |
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− | Debugging of Cortex-A72, Cortex-A53 and Cortex-M4 cores is enabled after primary boot stage.<br> |
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− | A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images packed in containers. |
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− | After the boot stage J-Link can be attached to a running target. |
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+ | ==External Boot Devices== |
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− | {{Note|After reset a watchdog timer is enabled. System Controller firmware is responsible to pereodicaly refresh the timer. |
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+ | Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface. |
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− | }} |
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+ | |||
+ | ==Watchdog Handling== |
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+ | System controller firmware handles watchdog during boot and programming of boot devices. |
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+ | |||
+ | ==Multi-Core Support== |
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+ | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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+ | The i.MX 8 family comes with a variety of multi-core options listed in the following table:<br> |
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+ | {| class="seggertable" |
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+ | |- |
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+ | ! Core || J-Link Support |
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+ | |- |
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+ | | 2 x Cortex-A72 ||style="text-align:center;"| {{NO}} |
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+ | |- |
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+ | | 4 x Cortex-A53 ||style="text-align:center;"| {{NO}} |
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+ | |- |
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+ | | 2 x Cortex-M4F ||style="text-align:center;"| {{YES}} |
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+ | |- |
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+ | | 1 x HIFI4 DSP ||style="text-align:center;"| {{NO}} |
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+ | |- |
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+ | |} |
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+ | The i.MX 8 family processors have additional cores: |
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+ | *System Controller Unit (SCU) Cortex-M4 - responsible for system initialization and boot, power and resource management, pad configuration. |
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+ | *Security Controller (SECO) Cortex-M0 - implements various security and cryptography functions. |
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+ | |||
+ | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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+ | ===Cortex-M4F core(s)=== |
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+ | ====Init/Setup==== |
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+ | The core(s) are enabled by SCU after boot. |
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+ | ====Reset==== |
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+ | Core reset is performed by SCU. |
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+ | ====Attach==== |
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+ | Attach is supported. |
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+ | |||
+ | ==Device Specific Handling== |
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+ | ===Connect=== |
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+ | Debugging of Cortex-M4 cores is enabled after primary boot stage. |
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+ | A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images. After the boot stage J-Link can be attached to a running target. |
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+ | ===Reset=== |
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+ | J-Link does not support reset of particular cores, as it is controlled by SCU. |
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+ | |||
+ | ==Evaluation Boards== |
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+ | *[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]] |
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+ | |||
+ | ==Example Application== |
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+ | *[[WikiTemplateEvalBoard#Example_Project | [SiliconVendor] [EvalBoardName]]] |
Revision as of 16:11, 5 April 2024
The NXP i.MX 8 are embedded multi-core processors consisting of two Cortex-M4, four Cortex-A53 and two Cortex-A72.
Contents
External Boot Devices
Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface.
Watchdog Handling
System controller firmware handles watchdog during boot and programming of boot devices.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8 family comes with a variety of multi-core options listed in the following table:
Core | J-Link Support |
---|---|
2 x Cortex-A72 | |
4 x Cortex-A53 | |
2 x Cortex-M4F | |
1 x HIFI4 DSP |
The i.MX 8 family processors have additional cores:
- System Controller Unit (SCU) Cortex-M4 - responsible for system initialization and boot, power and resource management, pad configuration.
- Security Controller (SECO) Cortex-M0 - implements various security and cryptography functions.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-M4F core(s)
Init/Setup
The core(s) are enabled by SCU after boot.
Reset
Core reset is performed by SCU.
Attach
Attach is supported.
Device Specific Handling
Connect
Debugging of Cortex-M4 cores is enabled after primary boot stage. A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images. After the boot stage J-Link can be attached to a running target.
Reset
J-Link does not support reset of particular cores, as it is controlled by SCU.