NXP i.MX 8

Debugging

Debugging of Cortex-A72, Cortex-A53 and Cortex-M4 cores is enabled after primary boot stage.
A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images packed in containers. After the boot stage J-Link can be attached to a running target.

Note:

After reset a watchdog timer is enabled. System Controller firmware is responsible to pereodicaly refresh the timer.