Difference between revisions of "NXP i.MX 8M Nano"
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The '''NXP i.MX 8M Nano''' are embedded multi-core processors consisting of one Cortex-M7 and up to four Cortex-A53. |
The '''NXP i.MX 8M Nano''' are embedded multi-core processors consisting of one Cortex-M7 and up to four Cortex-A53. |
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! Core || J-Link Support |
! Core || J-Link Support |
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| − | | 4 x Cortex-A53 ||style="text-align:center;"| {{ |
+ | | 4 x Cortex-A53 ||style="text-align:center;"| {{YES}} |
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| 1 x Cortex-M7 ||style="text-align:center;"| {{YES}} |
| 1 x Cortex-M7 ||style="text-align:center;"| {{YES}} |
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In below, the debug related multi-core behavior of the J-Link is described for each core: |
In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| + | ===Cortex-A53 core(s)=== |
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| + | ====Init/Setup==== |
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| + | The core(s) are enabled after boot. |
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| + | ====Reset==== |
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| + | Core reset is not performed. |
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| + | ====Attach==== |
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| + | Attach is supported. |
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===Cortex-M7 core(s)=== |
===Cortex-M7 core(s)=== |
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Latest revision as of 13:07, 15 May 2024
The NXP i.MX 8M Nano are embedded multi-core processors consisting of one Cortex-M7 and up to four Cortex-A53.
Contents
External Boot Devices
Programming of external boot media(eMMC, SDHC, QSPI/NAND Flash) is supported natively through USB Serial interface.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MX 8M Nano family comes with a variety of multi-core options listed in the following table:
| Core | J-Link Support |
|---|---|
| 4 x Cortex-A53 | 
|
| 1 x Cortex-M7 |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A53 core(s)
Init/Setup
The core(s) are enabled after boot.
Reset
Core reset is not performed.
Attach
Attach is supported.
Cortex-M7 core(s)
Init/Setup
The core(s) are enabled after boot. During connect the M7 is set to execute an endless loop at 0x00000000 (TCM RAM).
Reset
Reset is performed by using device-specific registers, than target CPU is halted.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions.
Device Specific Handling
Connect
After the boot stage J-Link writes an "infinite loop" code to the start of the M7s TCM RAM.
