NXP iMXRT1180
The NXP i.MXRT1180 (RT1180) series features a high performance Cortex-M7 core and a power efficient Cortex-M33 core.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| FlexSPI 1 | 0x38000000 | Up to 128 MB | 
|
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports the pin configuration used on the X-MIMXRT1180-EVK.
ECC RAM
The J-Link initializes the M33 System TCM RAM @ 0x20000000 (128 KB) which is used as work RAM during flash programming on connect.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The RT1180 family comes with a Cortex-M33 (main core) and a Cortex-M7 (secondary core). After reset / by default, the Cortex-M7 is disabled.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see NXP_i.MXRT1180_ECC_RAM
Reset
- No reset is performed.
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the secondary core is not enabled yet, it will be enabled / released from reset
- If it's already enabled, a simple attach will be performed
Reset
- No reset is performed.
Attach
- Attach is supported / desired
Limitations
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Evaluation Boards
- NXP X-MIMXRT1180-EVK: http://wiki.segger.com/NXP_X-MIMXRT1180-EVK
Example Application
- NXP X-MIMXRT1180-EVK: http://wiki.segger.com/NXP_X-MIMXRT1180-EVK#Example_Project
