NXP iMXRT1180

The NXP i.MXRT1180 (RT1180) series features a high performance Cortex-M7 core and a power efficient Cortex-M33 core.

Flash Banks

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports the pin configuration used on the X-MIMXRT1180-EVK. Flash programming is supported via Cortex-M33 as well as Cortex-M7.

Flash Bank	Base address	Size	J-Link Support
FlexSPI 1 (NS)	0x28000000	Up to 128 MB	(1)
FlexSPI 1 (S)	0x38000000	Up to 128 MB	(1)

Note:
For now, the flash loader does not restore the clock configuration, pin configuration and FlexSPI1 configuration because the current SDK templates do not come with valid boot headers thus expect that the flash loader initializes everything so that the flash is memory mapped accessible. This may cause problems with specific custom applications because the peripherals mentioned above do not contain reset values on debug session start but are initialized by the flash loader.

ECC RAM

ECC RAM needs to be initialized before it can be used. By default, the J-Link initializes RAM regions which are required for the initial connect to the target only. For the RT1180 series, the initialized regions depend on the selected core. For details, please refer to the sections below. Please note that reading to uninitialized regions result in ECC errors.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The RT1180 family comes with a Cortex-M33 (main core) and a Cortex-M7 (secondary core). After reset / by default, the Cortex-M7 is disabled. In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

• Initiate the M33 System TCM RAM @ 0x20000000 (128 KB) which is used as work RAM during flash programming on connect.

Reset

• No reset is performed.

Attach

• Attach is not supported because the J-Link initializes certain RAM regions by default

Secondary core(s)

Init/Setup

• If the secondary core is not enabled yet:
  • it will be enabled / released from reset
  • The M33 System ITCM RAM @ 0x00000000 (128 KB) which is used as work RAM during flash programming on connect will be initialized
• If it's already enabled, a simple attach will be performed

Reset

• No reset is performed.

Attach

• Attach is supported / desired

Evaluation Boards

• NXP X-MIMXRT1180-EVK: NXP X-MIMXRT1180-EVK

Example Application

• NXP X-MIMXRT1180-EVK: NXP X-MIMXRT1180-EVK#Example Project