Difference between revisions of "Nations N32G03x"
(Created page with "__TOC__ The '''Nations N32G032x''' are general-purpose microcontroller based on the Arm® Cortex®-M0 core. ==Flash Banks== ===Internal Flash=== {| class="seggertable" |- ! F...") |
|||
(5 intermediate revisions by the same user not shown) | |||
Line 8: | Line 8: | ||
! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
||
|- |
|- |
||
− | | Main Flash || 0x08000000 || Up to 64 KB || style="text-align:center;"| {{YES}} |
+ | | Main Flash || style="text-align:center;"| 0x08000000 || style="text-align:center;"| Up to 64 KB || style="text-align:center;"| {{YES}} |
− | |} |
||
− | |||
− | ====ECC Flash [OPTIONAL]==== |
||
− | *Describe ECC Flash restriction here. |
||
− | |||
− | ===QSPI Flash=== |
||
− | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
||
− | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
||
− | {| class="seggertable" |
||
|- |
|- |
||
+ | | Option Byte || style="text-align:center;"| 0x1FFFF600|| style="text-align:center;"| 16 B || style="text-align:center;"| {{YES}} |
||
− | ! Device !! Base address !! Maximum size !! Supported pin configuration |
||
− | |- |
||
− | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
||
− | *'''[LOADER_NAME]''' |
||
− | *[LOADER_NAME] |
||
− | *[LOADER_NAME] |
||
|} |
|} |
||
− | |||
− | ==ECC RAM [OPTIONAL]== |
||
− | *Describe ECC RAM restriction here. |
||
− | |||
− | ==Vector Table Remap [OPTIONAL]== |
||
− | *Describe Vector Table Remap here.. |
||
− | |||
− | ==Multi-Core Support [OPTIONAL]== |
||
− | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]]. |
||
− | The S32K3 family comes with a variety of multi-core options. Some devices from this family feature a secondary core which is disabled after reset / by default. Some of the are available with enabled ''lockstep'' mode, only. In below, the debug related multi-core behavior of the J-Link is described for each core: |
||
− | ===Main core=== |
||
− | ====Init/Setup==== |
||
− | *Initializes the ECC RAM, see [[XXX | XXX]] |
||
− | *Enables debugging |
||
− | ====Reset==== |
||
− | *Device specific reset is performed, see [[XXX | XXX]] |
||
− | ====Attach==== |
||
− | *Attach is not supported because the J-Link initializes certain RAM regions by default |
||
− | ===Secondary core(s)=== |
||
− | ====Init/Setup==== |
||
− | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
||
− | *If the secondary core is not enabled yet, it will be enabled / release from reset |
||
− | ====Reset==== |
||
− | No reset is performed. |
||
− | ====Attach==== |
||
− | *Attach is supported / desired |
||
− | |||
==Device Specific Handling== |
==Device Specific Handling== |
||
===Reset=== |
===Reset=== |
||
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
||
− | *The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
||
− | *The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
||
− | *The device uses custom reset:..... |
||
− | |||
− | ==Limitations== |
||
− | ===Dual Core Support=== |
||
− | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
||
− | |||
− | ===Attach=== |
||
− | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
||
==Evaluation Boards== |
==Evaluation Boards== |
||
− | * |
+ | *Nations N32G030C8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G030C8L7_STB |
+ | *Nations N32G031C8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G031C8L7_STB |
||
+ | *Nations N32G032R8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G032R8L7_STB |
||
==Example Application== |
==Example Application== |
||
− | * |
+ | *Nations N32G030C8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G030C8L7_STB#Example_Project |
+ | *Nations N32G031C8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G031C8L7_STB#Example_Project |
||
+ | *Nations N32G032R8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G032R8L7_STB#Example_Project |
Latest revision as of 13:09, 15 February 2023
Contents
The Nations N32G032x are general-purpose microcontroller based on the Arm® Cortex®-M0 core.
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Main Flash | 0x08000000 | Up to 64 KB | |
Option Byte | 0x1FFFF600 | 16 B |
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Evaluation Boards
- Nations N32G030C8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G030C8L7_STB
- Nations N32G031C8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G031C8L7_STB
- Nations N32G032R8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G032R8L7_STB
Example Application
- Nations N32G030C8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G030C8L7_STB#Example_Project
- Nations N32G031C8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G031C8L7_STB#Example_Project
- Nations N32G032R8L7_STB evaluation board: https://wiki.segger.com/Nations_N32G032R8L7_STB#Example_Project