RISC-V
RISC-V is an open source CPU specification. RISC-V is not a single CPU, it is merely a standard which RISC-V devices have to follow. RISC-V is maintained by the RISC-V foundation (https://riscv.org). All relevant documents are in the public domain. There are various different CPU cores defined. The word is not fixed, it can range from 32-bits to 128bits. In reality, most implementations are 32-bit (RV32) or 64-bit (RV64). RISC-V is an alternative to the ARM architecture, owned by ARM (http://www.arm.com). ARM cores are designed and licensed by ARM only. The licensees are bound by the restrictive license terms and usually pay significant license fees.
ISA Variants
Numerous ISA (Instruction Set Architecture) variants are defined by the specification. The most common ones are:
ISA Name | Explanation |
---|---|
RV32I | Basic 32-bit CPU with integer capabilities and 32 General purpose registers, no multiply / divide instruction. |
RV32E | Basic 32-bit CPU with integer capabilities and 16 General purpose registers, no multiply / divide instruction. |
Available implementations
There are various implementations available from different sources. Some implementations can be freely used, others are commercial.
Vendors
- SiFive http://www.sifive.com
- Andes Technology http://www.andestech.com
Debug interface
There is draft debug standard defined by the RISC-V foundation. However, this debug standard defines only JTAG, no cJTAG or SWD access and is not followed by every vendor See https://github.com/riscv/riscv-debug-spec
References
- RISC-V Foundation https://riscv.org
- ISA specification https://riscv.org/2019/07/risc-v-foundation-announces-ratification-of-the-risc-v-base-isa-and-privileged-architecture-specifications/
- Official debug spec https://github.com/riscv/riscv-debug-spec