RISC-V
RISC-V is an open source CPU specification. RISC-V is not a single CPU, it is merely a standard which RISC-V devices have to follow. RISC-V is maintained by the RISC-V foundation (https://riscv.org). All relevant documents are in the public domain. There are various different CPU cores defined. The word is not fixed, it can range from 32-bits to 128bits. In reality, most implementations are 32-bit (RV32) or 64-bit (RV64). RISC-V is an alternative to the ARM architecture, owned by ARM (http://www.arm.com). ARM cores are designed and licensed by ARM only. The licensees are bound by the restrictive license terms and usually pay significant license fees.
Contents
ISA Variants
Numerous ISA (Instruction Set Architecture) variants are defined by the specification. The most common ones are:
| ISA Name | Explanation |
|---|---|
| RV32I | Basic 32-bit CPU with 32 general purpose registers, no multiply / divide instruction. |
| RV32ICM | RV32I + Compressed instruction support + multiply / divide instructions. |
| RV32E | Basic 32-bit CPU with integer capabilities and 16 General purpose registers, no multiply / divide instruction. |
| RV32ECM | RV32E + Compressed instruction support + multiply / divide instructions. |
ISA extensions
There are various optional extensions, available in the Machine ISA Register misa (-> 3.1.1 of spec)
| Bit | Character | Description |
|---|---|---|
| 0 | A | Atomic extensions |
| 1 | B | Bit manipulation extensions (tentative) |
| 2 | C | Compressed extension (More efficient encoding of instructions, reducing code size) |
| 3 | D | Double-precision floating-point extension |
| 4 | E | RV32E, "Embedded" base ISA (not an extension). Means 16 general purpose registers only, in contrast to the I-variant |
| 5 | F | Single-precision floating-point extension |
| 6 | G | Additional standard extensions present |
| 7 | H | Hypervisor extension |
| 8 | I | Base "integer" ISA variant for 32-register cores RV32I, RV64I, RV128I. Not an extension. In contrast to the E-variant. |
| 9 | J | Tentatively reserved for Dynamically Translated Languages extension |
| 10 | K | Reserved |
| 11 | L | Tentatively reserved for Decimal Floating-Point extension |
| 12 | M | Integer Multiply/Divide extension |
| 13 | N | User-level interrupts supported |
| 14 | O | Reserved |
| 15 | P | Tentatively reserved for Packed-SIMD extension |
| 16 | Q | Quad-precision floating-point extension |
| 17 | R | Reserved |
| 18 | S | Supervisor mode implemented |
| 19 | T | Transactional Memory extension (tentative) |
| 20 | U | User mode implemented |
| 21 | V | Vector extension (tentative) |
Available implementations
There are various implementations available from different sources. Some implementations can be freely used, others are commercial.
Vendors
- SiFive http://www.sifive.com
- Andes Technology http://www.andestech.com
Debug interface
There is draft debug standard defined by the RISC-V foundation. However, this debug standard defines only JTAG, no cJTAG or SWD access and is not followed by every vendor See https://github.com/riscv/riscv-debug-spec
References
- RISC-V Foundation https://riscv.org
- ISA specification https://riscv.org/2019/07/risc-v-foundation-announces-ratification-of-the-risc-v-base-isa-and-privileged-architecture-specifications/
- Official debug spec https://github.com/riscv/riscv-debug-spec
