Difference between revisions of "RZ/G1"
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A debug session on the main core, running the J-Link script file from below, is needed to enable access to the second core. |
A debug session on the main core, running the J-Link script file from below, is needed to enable access to the second core. |
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Then a debug session on the second core, using the other script below, can be started. |
Then a debug session on the second core, using the other script below, can be started. |
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| + | *[[File:Renesas_RZG1_ConnectCore0_EnableCore1.JLinkScript]] |
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| + | *[[File:Renesas_RZG1_ConnectCore1.JLinkScript]] |
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Revision as of 14:42, 14 October 2015
The Renesas RZ/G1 is a dual core Cortex-A15 device. By default, only one Cortex-A15 core is running which needs to release the second core from reset from within the application running on the main core.
Due to design limitations of the device, the second core cannot be easily enabled independently from the main core, via J-Link. A debug session on the main core, running the J-Link script file from below, is needed to enable access to the second core. Then a debug session on the second core, using the other script below, can be started.
