Difference between revisions of "Realtek Ameba D"
| Line 19: | Line 19: | ||
! Device !! Base address !! Maximum size !! Supported pin configuration |
! Device !! Base address !! Maximum size !! Supported pin configuration |
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|- |
|- |
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| − | | RTL872xCS |
+ | | RTL872xCS <br> |
| − | RTL872xDN |
+ | RTL872xDN <br> |
RTL872xDM |
RTL872xDM |
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|| 0x08000000 || 16 MB || |
|| 0x08000000 || 16 MB || |
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| Line 27: | Line 27: | ||
| − | ==Multi-Core Support |
+ | ==Multi-Core Support== |
Flash programming is done by KM0 core (Cortex-M23).<br> |
Flash programming is done by KM0 core (Cortex-M23).<br> |
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| − | |||
| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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| − | |||
| − | ==Device Specific Handling== |
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| − | ===Reset=== |
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| − | *The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | |||
| − | |||
| − | ==Limitations== |
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| − | ===Dual Core Support=== |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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| − | |||
==Evaluation Boards== |
==Evaluation Boards== |
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Revision as of 12:34, 6 March 2023
Contents
The Realtek Ameba D are dual core (KM0/KM4) microprocessors with WIFI and Bluetooth.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support | Limitations |
|---|---|---|---|---|
| QSPI | 0x08000000 | 4 MB |  |
only for RTL872xDF devices |
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| RTL872xCS RTL872xDN |
0x08000000 | 16 MB |
|
Multi-Core Support
Flash programming is done by KM0 core (Cortex-M23).
Evaluation Boards
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
Example Application
- [SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
