Realtek Ameba D

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The Realtek Ameba D are dual core (KM0/KM4) microprocessors with WIFI and Bluetooth.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support Limitations
QSPI 0x08000000 4 MB YES.png only for RTL872xDF devices


QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in bold.

Device Base address Maximum size Supported pin configuration
RTL872xCS

RTL872xDN RTL872xDM

0x08000000 16 MB
  • Default SCK@B13 CS@B16 D0@B14 D1@B17


Multi-Core Support [OPTIONAL]

Flash programming is done by KM0 core (Cortex-M23).

The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

  • Initializes the ECC RAM, see XXX
  • Enables debugging

Reset

  • Device specific reset is performed, see XXX

Attach

  • Attach is not supported because the J-Link initializes certain RAM regions by default

Secondary core(s)

Init/Setup

  • If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
  • If the secondary core is not enabled yet, it will be enabled / release from reset

Reset

No reset is performed.

Attach

  • Attach is supported / desired

Device Specific Handling

Reset

  • The devices uses normal Cortex-M reset, no special handling necessary, like described here.


Limitations

Dual Core Support

Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.


Evaluation Boards

Example Application