Renesas ASSP EASY

The Renesas ASSP easy are RISC-V based microcontrollers.

Flash Banks

Internal Flash

Flash Bank	Base address	Size	J-Link Support
Code Flash	0x00000000	up to 128 KB
Config Flash	0x01010008	up tp 44 B
Data Flash	0x40100000	4 KB

ECC RAM

• Device has ECC RAM which has to be initialized before use.

Watchdog Handling

• The device does not have a watchdog.
• The device has a watchdog [WATCHDOGNAME].
• The watchdog is fed during flash programming.
• If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.

Multi-Core Support [OPTIONAL]

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

• Initializes the ECC RAM, see XXX
• Enables debugging

Reset

• Device specific reset is performed, see XXX

Attach

• Attach is not supported because the J-Link initializes certain RAM regions by default

Secondary core(s)

Init/Setup

• If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
• If the secondary core is not enabled yet, it will be enabled / release from reset

Reset

No reset is performed.

Attach

• Attach is supported / desired

Device Specific Handling

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.
• The device uses Cortex-M Core reset, no special handling necessary, like described here.
• The device uses Cortex-M Rest Pin, no special handling necessary, like described here.
• The device uses Cortex-A reset, no special handling necessary, like described here.
• The device uses Cortex-R reset, no special handling necessary, like described here.
• The device uses ARMv8-A reset, no special handling necessary, like described here.
• The device uses ARMv8-R reset, no special handling necessary, like described here.
• The device uses custom reset:.....

Limitations

Dual Core Support

Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.

Attach

Attach is not supported by default because the J-Link initializes certain RAM regions by default.

Evaluation Boards

• [SiliconVendor] [EvalBoardName]

Example Application

• [SiliconVendor] [EvalBoardName]