Renesas ASSP EASY
Revision as of 17:30, 18 March 2024 by Torben.scharping (talk | contribs) (→Multi-Core Support [OPTIONAL])
The Renesas ASSP easy are RISC-V based microcontrollers.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Code Flash | 0x00000000 | up to 128 KB | |
Config Flash | 0x01010008 | up tp 44 B | |
Data Flash | 0x40100000 | up to 4 KB |
ECC RAM
- Device has ECC RAM which has to be initialized before use.
Watchdog Handling
- The device does not have a watchdog.
- The device has a watchdog [WATCHDOGNAME].
- The watchdog is fed during flash programming.
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Device Specific Handling
Connect
Reset
- The device uses normal RISC-V reset, no special handling necessary, like described here.
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.