Difference between revisions of "Renesas FPB-R9A02G021"
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*Power the board via J17. |
*Power the board via J17. |
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* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
* Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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| − | [[File:Renesas_FPB-R9A02G021_R9A02G021_connect. |
+ | [[File:Renesas_FPB-R9A02G021_R9A02G021_connect.png|400px]] |
== Example Project== |
== Example Project== |
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Latest revision as of 12:13, 19 March 2024
This article describes specifics for the Renesas FPB-R9A02G021 evaluation board.
Preparing for J-Link
- Connect the J-Link to J15.
- Power the board via J17.
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the Renesas FPB-R9A02G021.
It is a simple Hello World sample linked into the internal flash.
SETUP
- Embedded Studio RISC-V: V7.20
- Hardware: Renesas FPB-R9A02G021
- Link: File:Renesas Sapporo5 R9A02G021 TestProject ES RV 7V20.zip
