Difference between revisions of "Renesas RZ/A3UL SMARC EVK"
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This article describes specifics for the Renesas RZ/A3UL SMARC evaluation board. The board supports different boot / power modes. |
This article describes specifics for the Renesas RZ/A3UL SMARC evaluation board. The board supports different boot / power modes. |
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[[File:Renesas_RZ_A3UL_SMARC_EVK.jpg|450px]] |
[[File:Renesas_RZ_A3UL_SMARC_EVK.jpg|450px]] |
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== Minimum requirements == |
== Minimum requirements == |
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* J-Link software V7.70a or later |
* J-Link software V7.70a or later |
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== Preparing for J-Link == |
== Preparing for J-Link == |
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+ | *'''Make sure that SW1-1 == OFF (default is ON). This is necessary to enable debugging.''' |
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*Connect the J-Link to the SWD header (CN2) |
*Connect the J-Link to the SWD header (CN2) |
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*Power the board via USB-C (5V / 3A) |
*Power the board via USB-C (5V / 3A) |
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*Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
*Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: |
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[[File:Renesas_RZ_A3UL_SMARC_Connect.PNG|400px]] |
[[File:Renesas_RZ_A3UL_SMARC_Connect.PNG|400px]] |
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== Example Project== |
== Example Project== |
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*N/A |
*N/A |
Latest revision as of 15:33, 8 May 2024
This article describes specifics for the Renesas RZ/A3UL SMARC evaluation board. The board supports different boot / power modes.
Minimum requirements
- J-Link software V7.70a or later
Preparing for J-Link
- Make sure that SW1-1 == OFF (default is ON). This is necessary to enable debugging.
- Connect the J-Link to the SWD header (CN2)
- Power the board via USB-C (5V / 3A)
- Press the POWER button for a few seconds until the Carrier PWR On led turns on
- Verify the Connection with e.g. J-Link Commander. The output should look as follows:
Example Project
- N/A