Renesas RZ/G3S
Contents
The Renesas RZ/G3S series includes includes a Cortex-A55 as well as two Cortex-M33 cores.
Flash Banks
Internal Flash
The device does not feature internal flash.
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in bold.
Device | Base address | Maximum size | Supported pin configuration | ||||
---|---|---|---|---|---|---|---|
External QSPI flash (secure) | [0x80000000] | 256 MB |
|
External QSPI flash (non-secure) | [0x90000000] | 256 MB |
|
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:
CM33_0
Init/Setup
If the CM33 is held in reset, J-Link releases the core from reset and let it execute a while (1) code located at 0x00120000.
Reset
- Device specific reset is performed:
J-Link executing the reset sequence specified by Renesas. This reset is basically a reset via reset pin followed by the release CM33 from reset sequence. After reset, the CPU is halted in the while (1) loop located at 0x00120000.
Attach
- Attach is possible in case of the CM33 core is clocked and released from reset
CM33_1
Init/Setup
If the CM33 is held in reset, J-Link releases the core from reset and let it execute a while (1) code located at 0x00120000.
Reset
- Device specific reset is performed:
J-Link executing the reset sequence specified by Renesas. This reset is basically a reset via reset pin followed by the release CM33 from reset sequence. After reset, the CPU is halted in the while (1) loop located at 0x00120000.
Attach
- Attach is possible in case of the CM33 core is clocked and released from reset
Device Specific Handling
Limitations
Cortex-A55
J-Link does not support the Cortex-A55.
Evaluation Boards
- Renesas RZ/G3S SMARC Evaluation Board Kit
Example Application
Evaluation Boards
- Renesas RZ/G3S SMARC Evaluation Board Kit [Renesas] [RZ/G3S SMARC Evaluation Board Kit]
Example Application
- Renesas RZ/G3S SMARC Evaluation Board Kit [Renesas] [RZ/G3S SMARC Evaluation Board Kit]