Difference between revisions of "Renesas RZ/V2L"
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==Specifics== |
==Specifics== |
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==Connect== |
==Connect== |
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− | By default, the Cortex-M33 core is not enabled. In order to establish a connection, the J-Link performs a device specific connect sequence. After executing the sequence, the Cortex-M33 is executing a test loop in the SRAM. |
+ | By default, the Cortex-M33 core is not enabled. In order to establish a connection, the J-Link performs a device specific connect sequence. After executing the sequence, the Cortex-M33 is executing a test loop in the SRAM. This way, the Cortex-M33 can be debugged out-of-the-box without the need of having a application running on the main core which enables the Cortex-M33. |
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==Reset== |
==Reset== |
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A device specific reset is performed which resets the M33 + performs the Cortex-M33 enable sequence. The Cortex-A55 is not affected by the reset. |
A device specific reset is performed which resets the M33 + performs the Cortex-M33 enable sequence. The Cortex-A55 is not affected by the reset. |
Revision as of 16:46, 4 November 2021
The Renesas RZ/V2L is equipped with a Cortex-A55 (dual or single) CPU + a Cortex-M33 CPU.
Specifics
Connect
By default, the Cortex-M33 core is not enabled. In order to establish a connection, the J-Link performs a device specific connect sequence. After executing the sequence, the Cortex-M33 is executing a test loop in the SRAM. This way, the Cortex-M33 can be debugged out-of-the-box without the need of having a application running on the main core which enables the Cortex-M33.
Reset
A device specific reset is performed which resets the M33 + performs the Cortex-M33 enable sequence. The Cortex-A55 is not affected by the reset.
Limitations
The J-Link software supports the Cortex-M33 core, only.
Evaluation Boards
TBD
Example Application
TBD