Difference between revisions of "ST SR6P6"

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__TOC__
  
__TOC__
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The '''ST SR6P6xx''' are Stellar P series microcontroler, which inlcudes 6 Cortex-R52+ and 3 Cortex-M4.
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The '''ST SR6P6xx''' are Stellar P series microcontroler, which inlcude 10 Cortex-R52+ and 3 Cortex-M4.
 
==Flash Banks==
  
==Flash Banks==
 
===Internal Flash===
  
===Internal Flash===
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| RWW Partition 4 || 0x28800000 || 2048 KB || style="text-align:center;"| {{YES}}
 
| RWW Partition 4 || 0x28800000 || 2048 KB || style="text-align:center;"| {{YES}}
 
|-
  
|-
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| RWW Partition 5 || 0x28A00000 || 2048 KB || style="text-align:center;"| {{YES}}
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| RWW Partition 5 || 0x28C00000 || 2048 KB || style="text-align:center;"| {{YES}}
 
|-
  
|-
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| RWW Partition 6 || 0x28C00000 || 2048 KB || style="text-align:center;"| {{YES}}
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| RWW Partition 6 || 0x29000000 || 2048 KB || style="text-align:center;"| {{YES}}
 
|-
  
|-
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| RWW Partition 7 || 0x28E00000 || 2048 KB || style="text-align:center;"| {{YES}}
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| RWW Partition 7 || 0x29400000 || 2048 KB || style="text-align:center;"| {{YES}}
 
|-
  
|-
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| RWW Partition 8 || 0x29000000 || 2048 KB || style="text-align:center;"| {{YES}}
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| EEPROM / RWW 8 || 0x29E00000|| 512 KB || style="text-align:center;"| {{YES}}
 
|-
  
|-
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| RWW Partition 9 || 0x29400000 || 2048 KB || style="text-align:center;"| {{YES}}
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| UTEST / RWW 1 || 0x29F80000|| 32 KB || style="text-align:center;"| {{YES}}
 
|-
  
|-
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| EEPROM / RWW 10 || 0x29E00000|| 512 KB || style="text-align:center;"| {{YES}}
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| Boot Code Sector / RWW 1 || 0x29FB8000|| 16 KB || style="text-align:center;"| {{YES}}
 
|-
  
|-
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| UTEST || 0x29F80000|| 32 KB || style="text-align:center;"| {{YES}}
 +
| HSM Code / RWW 9/10 || 0x00000000 || 512 KB || style="text-align:center;"| {{NO}}
 
|-
  
|-
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| Boot Code Sector || 0x29FB8000|| 16 KB || style="text-align:center;"| {{YES}}
 +
| HSM Data / RWW 11 || 0x003A0000 || 128 KB || style="text-align:center;"| {{NO}}
 
|-
  
|-
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| HSM Code / RWW 11 || 0x00000000 || 512 KB || style="text-align:center;"| {{NO}}
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| HSM UT / RWW 11 || 0x0037C000 || 16 KB || style="text-align:center;"| {{NO}}
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|-
  
−
| HSM Data / RWW 13 || 0x003A0000 || 128 KB || style="text-align:center;"| {{NO}}
 
−
|-
  
−
| HSM UT / RWW 13 || 0x0037C000 || 16 KB || style="text-align:center;"| {{NO}}
 
 
|}
  
|}
  +
  +
====Flash programming====
  +
Flash programming of all above listed flash regions is done through Cluster0 Core0 (Cortex-R52).<br>
  +
The flash controller has no explicit erase function. <br>
  +
When reprogramming flash an explicit erase before programming is not necessary. Already programmed flash can be directly reprogrammed.
   
 
====ECC Flash ====
  
====ECC Flash ====
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==ECC RAM ==
  
==ECC RAM ==
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Device has ECC RAM, init before first use is necessary.
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Device has ECC RAM, init before first use is necessary. Please refer to the reference Manual.
  +
ECC RAM initialization is done for Cluster 0 Core 0, see below.
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<!--
  
  +
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==Multi-Core Support [OPTIONAL]==
  
  +
==Multi-Core Support==
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Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].
  
  +
{{Template:ST_SR6Px_MultiCoreSupport|SR6P6|*Functional Reset is initiated for Cut 1.0 silicon.}}
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The S32K3 family comes with a variety of multi-core options. Some devices from this family feature a secondary core which is disabled after reset / by default. Some of the are available with enabled ''lockstep'' mode, only. In below, the debug related multi-core behavior of the J-Link is described for each core:
  
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===Main core===
  
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====Init/Setup====
  
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*Initializes the ECC RAM, see [[XXX | XXX]]
  
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*Enables debugging
  
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====Reset====
  
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*Device specific reset is performed, see [[XXX | XXX]]
  
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====Attach====
  
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*Attach is not supported because the J-Link initializes certain RAM regions by default
  
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===Secondary core(s)===
  
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====Init/Setup====
  
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*If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
  
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*If the secondary core is not enabled yet, it will be enabled / release from reset
  
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====Reset====
  
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No reset is performed.
  
−
====Attach====
  
−
*Attach is supported / desired
  
   
 
==Device Specific Handling==
  
==Device Specific Handling==
 
===Reset===
  
===Reset===
  +
* Depending on connected core, different resets are performed, see above.
−
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
  
−
*The devices uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]].
  
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*The devices uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]].
  
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*The device uses custom reset:.....
  
−  
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==Limitations==
  
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===Dual Core Support===
  
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Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
  
−  
−
===Attach===
  
−
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
  
   
 
==Evaluation Boards==
  
==Evaluation Boards==
  +
*[[ST SR6P6-EVBC8000P]]
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*[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard
  
−  
−
==Example Application==
  
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*[SiliconVendor] [EvalBoardName] evaluation board: http://techwiki.segger.local/WikiTemplateEvalBoard#Example_Project
  
−
--!>
  

Latest revision as of 11:32, 10 October 2023

The ST SR6P6xx are Stellar P series microcontroler, which inlcude 10 Cortex-R52+ and 3 Cortex-M4.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
RWW Partition 0 0x28000000 1792 KB YES.png
RWW Partition 1 0x281C0000 2048 KB YES.png
RWW Partition 2 0x28400000 1792 KB YES.png
RWW Partition 3 0x285C0000 2048 KB YES.png
RWW Partition 4 0x28800000 2048 KB YES.png
RWW Partition 5 0x28C00000 2048 KB YES.png
RWW Partition 6 0x29000000 2048 KB YES.png
RWW Partition 7 0x29400000 2048 KB YES.png
EEPROM / RWW 8 0x29E00000 512 KB YES.png
UTEST / RWW 1 0x29F80000 32 KB YES.png
Boot Code Sector / RWW 1 0x29FB8000 16 KB YES.png
HSM Code / RWW 9/10 0x00000000 512 KB NO.png
HSM Data / RWW 11 0x003A0000 128 KB NO.png
HSM UT / RWW 11 0x0037C000 16 KB NO.png

Flash programming

Flash programming of all above listed flash regions is done through Cluster0 Core0 (Cortex-R52).
The flash controller has no explicit erase function.
When reprogramming flash an explicit erase before programming is not necessary. Already programmed flash can be directly reprogrammed.

ECC Flash

Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.

ECC RAM

Device has ECC RAM, init before first use is necessary. Please refer to the reference Manual. ECC RAM initialization is done for Cluster 0 Core 0, see below.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6P6 family comes with 10 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled lockstep mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Cortex-R52 Cluster 0 Core 0

Init/Setup

  • WDT is enabled by default. If it is enabled, it will be disabled.

Reset

  • ARMv8-R Reset is performed like described here.
  • Functional Reset is initiated for Cut 1.0 silicon.
  • Initializes 256KB ECC RAM starting at 0x60000000
  • WDT is enabled by default. If it is enabled, it will be disabled.

Attach

  • Attach is supported, user has to take care about ECC RAM initialization.

Cortex-R52 Cluster 0 Core 1

Init/Setup

  • WDT is enabled by default. If it is enabled, it will be disabled.
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cortex-R52 Cluster 1 Core 0

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cortex-R52 Cluster 1 Core 1

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cortex-R52 Cluster 2 Core 0

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

DSPH Core

Init/Setup

  • none

Reset

  • Cortex-M Typ 0 normal reset is performed like described here.

Attach

  • Attach is supported

DME Core

Init/Setup

  • none

Reset

  • Cortex-M Typ 0 normal reset is performed like described here.

Attach

  • Attach is supported

Device Specific Handling

Reset

  • Depending on connected core, different resets are performed, see above.

Evaluation Boards

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