ST STM32H5

ST STM32H5

The ST STM32H5 are Cortex-M33 based MCUs.

Flash Banks

Internal Flash

Device	Base address	Size	J-Link Support
STM32H503EB	0x08000000	128 KB
STM32H503KB	0x08000000	128 KB
STM32H503CB	0x08000000	128 KB
STM32H503RB	0x08000000	128 KB
STM32H562AI	0x08000000	2048 KB
STM32H562II	0x08000000	2048 KB
STM32H562RI	0x08000000	2048 KB
STM32H562VI	0x08000000	2048 KB
STM32H562ZI	0x08000000	2048 KB
STM32H563AG	0x08000000	2048 KB
STM32H563AI	0x08000000	2048 KB
STM32H563IG	0x08000000	2048 KB
STM32H563II	0x08000000	2048 KB
STM32H563MI	0x08000000	2048 KB
STM32H563RG	0x08000000	2048 KB
STM32H563RI	0x08000000	2048 KB
STM32H563VG	0x08000000	2048 KB
STM32H563VI	0x08000000	2048 KB
STM32H563ZG	0x08000000	2048 KB
STM32H563ZI	0x08000000	2048 KB
STM32H573AI	0x08000000	2048 KB
STM32H573II	0x08000000	2048 KB
STM32H573MI	0x08000000	2048 KB
STM32H573RI	0x08000000	2048 KB
STM32H573VI	0x08000000	2048 KB
STM32H573ZI	0x08000000	2048 KB

ECC Flash

The flash is ECC protected. When programming code with J-Link, the device flash controller is set to automatically program the correct ECC values.

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.

Device	Base address	Maximum size	Supported pin configuration
STM32H56x STM32H57x	0x90000000	256MB	CLK@PF10_nCS@PG6_D0@PB1_D1@PD12_D2@PC2_D3@PD13_D4@NA_D5@NA_D6@NA_D7@NA

ECC RAM

The device family provides three RAM segments: SRAM1, SRAM2 and SRAM3.
J-Link uses SRAM1 during flash programming. SRAM2 and SRAM3 are ECC protected, while SRAM1 is not so no ECC initialization is necessary.

Device Specifc Handling

Reset

• The devices uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

• ST STM32H573I-DK evaluation board: https://wiki.segger.com/ST_STM32H573I-DK

Example Application

• ST STM32H573I-DK evaluation board: https://wiki.segger.com/ST_STM32H573I-DK#Example_Project