Difference between revisions of "ST STM32L5"

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This article describes device specifics of the ST STM32L5 series devices.
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The STM32L5 devices are Cortex-M33 based low power MCUs.
 
__TOC__
  
__TOC__
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== Dualbank Flash Programming ==
  
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The ST STM32L5 series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte ''DUALBANK''. By default, the value of this option byte is DUALBANK == 1, which means that the flash is configured as dual bank memory while DUALBANK == 0 means that the flash is configured as single bank memory flash. In dual-bank mode, the flash boot source can be switched between bank 1 or bank 2. In single-bank mode, flash always boots from bank 1. The total flash size is exactly the same for both modes. Another advantage of using DUALBANK is that both banks can be accessed in parallel (e.g. reading bank 1 while programming bank 2).
  
   
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=== Problem description ===
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== Flash ==
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The following flash regions are supported by J-Link.
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The flash algorithm has to behave differently, depending on the active flash bank mode configuration as the flash controller expects different page indices for the same destination address.
  
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{| class="seggertable"
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|-
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! Device !! State !! Range !! Total size
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|-
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!colspan="4"| Main flash memory
  +
|-
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|rowspan="2"| STM32L5xxxC || Secure || 0x0C00_0000 - 0x0C03_FFFF ||rowspan="2"| 256 KB
  +
|-
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| Non-secure || 0x0800_0000 - 0x0803_FFFF
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|-
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|rowspan="2"| STM32L5xxxE || Secure || 0x0C00_0000 - 0x0C07_FFFF ||rowspan="2"| 512 KB
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|-
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| Non-secure || 0x0800_0000 - 0x0807_FFFF
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|-
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!colspan="4"| QSPI programming<ref>See: [[#(Octa)SPI_support | (Octa)SPI support]]</ref>
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|-
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| All || --- || 0x9000_0000 - 0x903F_FFFF (max) || 4 MB (max)
  +
|}
  +
<references />
   
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=== Solution ===
 +
=== Dualbank Flash Programming ===
  +
The ST STM32L5 series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte ''DUALBANK''. By default, the value of this option byte is DUALBANK == 1, which means that the flash is configured as dual bank memory while DUALBANK == 0 means that the flash is configured as single bank memory flash. In dual-bank mode, the flash boot source can be switched between bank 1 or bank 2. In single-bank mode, flash always boots from bank 1. The total flash size is exactly the same for both modes. Another advantage of using DUALBANK is that both banks can be accessed in parallel (e.g. reading bank 1 while programming bank 2).
  +
==== Problem description ====
  +
The flash algorithm has to behave differently, depending on the active flash bank mode configuration as the flash controller expects different page indices for the same destination address.
  +
==== Solution ====
 
When using the J-Link flash loader, make sure that the flash controller is configured for dual bank flash layout (DUALBANK == 1), which is the default.
  
When using the J-Link flash loader, make sure that the flash controller is configured for dual bank flash layout (DUALBANK == 1), which is the default.
  +
  +
=== (Octa)SPI support ===
  +
The ST STM32L5 device series comes with a OCTASPI controller which allows memory mapped read accesses to any (Octa)SPI flash, connected to the Octa-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Octa-SPI interface.
  +
  +
=== Supported pin configurations ===
  +
(Octa)SPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br>
  +
J-Link supports multiple pin configurations for STM32L5. The default loader is marked in '''bold'''.
  +
{| class="seggertable"
  +
|-
  +
! Device family !! Pin configuration/loader name
  +
|-
  +
| STM32L5xxxx || '''CLK@PA3_nCS@PA2_D0@PB1_D1@PB0_D2@PA7_D3@PA6_D4@NA_D5@NA_D6@NA_D7@NA'''
  +
|}
  +
  +
== TrustZone ==
  +
Flash programming with TrustZone enabled (TZEN = 1) is supported.<br>
  +
RDP level 0 and 0.5 is also supported. The RAMCode is only usable with RDP level 0, for RDP level 0.5 a RAMless flashloader has to be used. This is a technical limitation. The J-Link software is not able to decide at runtime when to use the RAMCode or RAMless flashloader. If you want to use the RAMless flashloader for RDP 0.5, you have to add "_RAMLess" to the device name, e.g. use "STM32L552ZE_RAMLess" instead of "STM32L552ZE".
  +
Please note that a significantly lower programming speed has to be expected with the RAMless flashloader.
  +
  +
== Reset ==
  +
For the STM32L5 devices, the [[J-Link_Reset_Strategies#Type_0:_Normal | Cortex-M default reset strategy]] is used.
  +
  +
== Debug specific ==
  +
Please refer to the [[ST_STM32#Device_specific_connect | generic STM32 article]].
  +
  +
== Option byte programming ==
  +
Direct option byte programming is not (yet) implemented for the ST STM32L5.
  +
However, the same method used to lock/unlock the devices can be used as described in [[#Securing/unsecuring_the_device|Securing/unsecuring the device]] can be used to adjust any option bytes.
  +
  +
== Securing/unsecuring the device ==
  +
Please refer to the [[ST_STM32#MCU_Security | generic STM32 article]].

Latest revision as of 16:33, 29 February 2024

This article describes device specifics of the ST STM32L5 series devices. The STM32L5 devices are Cortex-M33 based low power MCUs.

Flash

The following flash regions are supported by J-Link.

Device State Range Total size
Main flash memory
STM32L5xxxC Secure 0x0C00_0000 - 0x0C03_FFFF 256 KB
Non-secure 0x0800_0000 - 0x0803_FFFF
STM32L5xxxE Secure 0x0C00_0000 - 0x0C07_FFFF 512 KB
Non-secure 0x0800_0000 - 0x0807_FFFF
QSPI programming[1]
All --- 0x9000_0000 - 0x903F_FFFF (max) 4 MB (max)
  1. ↑ See: (Octa)SPI support

Dualbank Flash Programming

The ST STM32L5 series devices come with a dual-bank flash memory. The layout of the dual-bank flash memory can be configured by the user through the option byte DUALBANK. By default, the value of this option byte is DUALBANK == 1, which means that the flash is configured as dual bank memory while DUALBANK == 0 means that the flash is configured as single bank memory flash. In dual-bank mode, the flash boot source can be switched between bank 1 or bank 2. In single-bank mode, flash always boots from bank 1. The total flash size is exactly the same for both modes. Another advantage of using DUALBANK is that both banks can be accessed in parallel (e.g. reading bank 1 while programming bank 2).

Problem description

The flash algorithm has to behave differently, depending on the active flash bank mode configuration as the flash controller expects different page indices for the same destination address.

Solution

When using the J-Link flash loader, make sure that the flash controller is configured for dual bank flash layout (DUALBANK == 1), which is the default.

(Octa)SPI support

The ST STM32L5 device series comes with a OCTASPI controller which allows memory mapped read accesses to any (Octa)SPI flash, connected to the Octa-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Octa-SPI interface.

Supported pin configurations

(Octa)SPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for STM32L5. The default loader is marked in bold.

Device family Pin configuration/loader name
STM32L5xxxx CLK@PA3_nCS@PA2_D0@PB1_D1@PB0_D2@PA7_D3@PA6_D4@NA_D5@NA_D6@NA_D7@NA

TrustZone

Flash programming with TrustZone enabled (TZEN = 1) is supported.
RDP level 0 and 0.5 is also supported. The RAMCode is only usable with RDP level 0, for RDP level 0.5 a RAMless flashloader has to be used. This is a technical limitation. The J-Link software is not able to decide at runtime when to use the RAMCode or RAMless flashloader. If you want to use the RAMless flashloader for RDP 0.5, you have to add "_RAMLess" to the device name, e.g. use "STM32L552ZE_RAMLess" instead of "STM32L552ZE". Please note that a significantly lower programming speed has to be expected with the RAMless flashloader.

Reset

For the STM32L5 devices, the Cortex-M default reset strategy is used.

Debug specific

Please refer to the generic STM32 article.

Option byte programming

Direct option byte programming is not (yet) implemented for the ST STM32L5. However, the same method used to lock/unlock the devices can be used as described in Securing/unsecuring the device can be used to adjust any option bytes.

Securing/unsecuring the device

Please refer to the generic STM32 article.

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