Difference between revisions of "ST STM32U5"

From SEGGER Wiki
Jump to: navigation, search
(Minimum requirements)
(Minimum requirements)
 
Line 84: Line 84:
 
* J-Link software version V7.66d or later
 
* J-Link software version V7.66d or later
 
* Ozone V3.26b or later (if streaming trace and / or the sample project from below shall be used)
 
* Ozone V3.26b or later (if streaming trace and / or the sample project from below shall be used)
* J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
+
* J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
   
 
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
 
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Latest revision as of 16:47, 11 August 2022

The ST STM32U5 series are 32-bit ultra low power microcontrollers based on the ARM Cortex-M33 processor.

Device family

The STM32U5 device family consists of several subfamilies: STM32U57xxx, STM32U58xxx, STM32U59xxx and STM32U5Axxx.

STM32U57xxx STM32U58xxx STM32U59xxx STM32U5Axxx
STM32U575AI STM32U585AI STM32U595ZJ STM32U5A5ZJ
STM32U575CI STM32U585CI STM32U599BJ STM32U5A9BJ
STM32U575OI STM32U585OI STM32U599NJ STM32U5A9NJ
STM32U575QI STM32U585QI
STM32U575RI STM32U585RI
STM32U575VI STM32U585VI
STM32U575ZI STM32U585ZI
STM32U575AG STM32U585AG
STM32U575CG STM32U585CG
STM32U575OG STM32U585OG
STM32U575QG STM32U585QG
STM32U575RG STM32U585RG
STM32U575VG STM32U585VG
STM32U575ZG STM32U585ZG

On-Chip Memory Regions

The internal flash consists of up to 4MiB of memory.

Device Flash size (MiB) Start address End address
STM32U5xxxG 1 0x08000000 0x080FFFFF
STM32U5xxxI 2 0x08000000 0x081FFFFF
STM32U5xxxJ 4 0x08000000 0x083FFFFF

QSPI support

The ST STM32U5xxx device series comes with a OCTASPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Octa-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Octa-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the pins used to connect the SPI flash are not defined. Different pins can be used for the same OCTASPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. Our flash algorithms are based on the pin configurations used on the official evaluation boards. For pin configuration, different from the one used in the example flash algorithm, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

For further information regarding this as well as the flash algorithm, please refer to the following pages:

Reset

No special reset is required.

TrustZone

Flash programming with TrustZone enabled (TZEN = 1) is supported.

RDP level 0 and 0.5 is also supported. The RAMCode is only usable with RDP level 0, for RDP level 0.5 a RAMless flashloader has to be used. This is a technical limitation. The J-Link software is not able to decide at runtime when to use the RAMCode or RAMless flashloader. If you want to use the RAMless flashloader for RDP 0.5, you have to add "_RAMLess" to the device name, e.g. use "STM32U599NJ_RAMLess" instead of "STM32U599NJ". Please note that a significantly lower programming speed has to be expected with the RAMless flashloader.

Example Application

The following example project was created with the SEGGER Embedded Studio project wizard and should run out-of-the-box on any ST STM32U5xxxx device. It is a simple for loop incrementing the integer i. The application is linked into the internal flash.
SETUP

Tracing on ST STM32U5

Tracing on ST STM32U575

The following project has been tested with the minimum requirements mentioned and a ST STM32U575I-EVAL evaluation board.

Minimum requirements

In order to use trace on the ST STM32U575 MCU devices, the following minimum requirements have to be met:

  • J-Link software version V7.66d or later
  • Ozone V3.26b or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Streaming trace

Example Project: ST_STM32U575I_EV_TraceSample.zip

Tested Hardware

ST STM32U575I-EVAL

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time
Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time