Difference between revisions of "ST STM32WL"
(Created page with "__TOC__ The STM32WL55/54/E5xx long-range wireless and ultra-low-power devices embed a powerful and ultra-low-power LPWAN-compliant radio solution, enabling the following modul...") |
m (Fabian moved page STM32WL5x Ex to ST STM32WL: Device family articles are supposed to be named <VendorName> <FamilyName>) |
||
| (4 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
__TOC__ |
__TOC__ |
||
| + | The ST STM32WL5/WLE devices are ultra-low-power long-range wireless MCUs. |
||
| − | The STM32WL55/54/E5xx long-range wireless and ultra-low-power devices embed a powerful and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations: LoRa®, (G)FSK, (G)MSK, and BPSK. |
||
| + | * The STM32WL5 are dual core devices with a Cortex-M4 as main core and an additional Cortex-M0. |
||
| + | * The STM32WLE are single core Cortex-M4 devices. |
||
| + | |||
| + | A list of ST STM32WL devices supported by J-Link can be found on the [https://www.segger.com/supported-devices/search/STM32WL SEGGER homepage]. |
||
| + | |||
==Internal Flash== |
==Internal Flash== |
||
===Supported Regions=== |
===Supported Regions=== |
||
| Line 9: | Line 14: | ||
*Option Bytes (0x1FFF7800 - 0x1FFF7FFF) |
*Option Bytes (0x1FFF7800 - 0x1FFF7FFF) |
||
For now, the J-Link supports the main memory, only. |
For now, the J-Link supports the main memory, only. |
||
| + | |||
==Evaluation Boards== |
==Evaluation Boards== |
||
*ST STM32WL55JC2 evaluation board: https://wiki.segger.com/ST_STM32WL55JC2 |
*ST STM32WL55JC2 evaluation board: https://wiki.segger.com/ST_STM32WL55JC2 |
||
==Example Application== |
==Example Application== |
||
| − | *ST STM32WL55JC2 evaluation board: |
+ | *ST STM32WL55JC2 evaluation board: [[File:ST_STM32WL55JC2_TestProject_ES_V510b.zip]] |
| − | |||
| − | Summary: |
||
| − | 255 |
||
| − | This is a minor edit |
||
| − | Watch this page |
||
| − | Please note that all contributions to SEGGER Wiki may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here. |
||
| − | You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see SEGGER Wiki:Copyrights for details). Do not submit copyrighted work without permission! |
||
| − | |||
| − | Editing help (opens in new window) |
||
| − | Navigation menu |
||
| − | SebastianTalkPreferencesWatchlistContributionsLog outPageDiscussionReadEditView historyWatch |
||
| − | More |
||
| − | Search |
||
| − | Search SEGGER Wiki |
||
| − | www.segger.com |
||
| − | SEGGER Blog |
||
| − | Navigation |
||
| − | Wiki Main page |
||
| − | Recent changes |
||
| − | Random page |
||
| − | Help |
||
| − | Tools |
||
| − | What links here |
||
| − | Related changes |
||
| − | Upload file |
||
| − | Special pages |
||
| − | Page information |
||
| − | Privacy PolicyAbout SEGGER WikiDisclaimersPowered by MediaWiki |
||
Latest revision as of 17:44, 21 November 2022
The ST STM32WL5/WLE devices are ultra-low-power long-range wireless MCUs.
- The STM32WL5 are dual core devices with a Cortex-M4 as main core and an additional Cortex-M0.
- The STM32WLE are single core Cortex-M4 devices.
A list of ST STM32WL devices supported by J-Link can be found on the SEGGER homepage.
Internal Flash
Supported Regions
The internal flash is divided into 3 different regions:
- Main memory (0x08000000 - 0x0803FFFF)
- System memory (0x1FFF0000 - 0x1FFF6FFF)
- OTP area (0x1FFF7000 - 0x1FFF73FF)
- Option Bytes (0x1FFF7800 - 0x1FFF7FFF)
For now, the J-Link supports the main memory, only.
Evaluation Boards
- ST STM32WL55JC2 evaluation board: https://wiki.segger.com/ST_STM32WL55JC2
Example Application
- ST STM32WL55JC2 evaluation board: File:ST STM32WL55JC2 TestProject ES V510b.zip
