Difference between revisions of "SemiDrive E31xx"
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==ECC RAM== |
==ECC RAM== |
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E31xx devices have ECC RAM which can be disabled. |
E31xx devices have ECC RAM which can be disabled. |
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| − | However, a connect to E31xx devices will initialize 128KB at 0x500000. |
+ | However, a connect to E31xx devices will initialize 128KB at 0x500000 (1MB at 0x400000 for E3110). |
==Reset== |
==Reset== |
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Revision as of 13:26, 24 May 2023
Contents
The SemiDrive E31xx are Cortex-R5 based MCUs.
Internal Flash
E31xx devices consist of a SIP and have an internal QSPI flash.
Therefore programming the internal flash requires special handling. For more information about this, please see the QSPI Flash Programming Support article.
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x10000000 | Up to 4 MB | 
|
ECC RAM
E31xx devices have ECC RAM which can be disabled. However, a connect to E31xx devices will initialize 128KB at 0x500000 (1MB at 0x400000 for E3110).
Reset
No device specific reset is necessary. The normal Cortex-R reset is performed.
See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices
