Difference between revisions of "SemiDrive E32xx"
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The SemiDrive E32xx are Cortex-R5 based MCUs. |
The SemiDrive E32xx are Cortex-R5 based MCUs. |
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| + | |||
| + | ==Internal Flash== |
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| + | |||
| + | E32xx devices consist of a SIP and have an internal QSPI flash. |
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| + | |||
| + | Therefore programming the internal flash requires special handling. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]]. |
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| + | |||
| + | {| class="seggertable" |
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| + | |- |
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| + | ! Flash Bank || Base address !! Size || J-Link Support |
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| + | |- |
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| + | | Main flash || 0x10000000 || Up to 4 MB || style="text-align:center;"| {{YES}} |
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| + | |} |
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| + | |||
| + | ==ECC RAM== |
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| + | E32xx devices have ECC RAM which can be disabled. |
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| + | However, a connect to E32xx devices will initialize 512KB at 0x500000 (1MB at 0x400000 for E3210). |
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| + | |||
| + | ==Reset== |
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| + | No device specific reset is necessary. The normal Cortex-R reset is performed. |
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| + | |||
| + | See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices |
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| + | |||
| + | <!-- |
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| + | ==Evaluation Boards== |
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| + | *NXP MCX-N9XX-EVK evaluation board: https://wiki.segger.com/NXP_MCX-N9XX-EVK |
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| + | |||
| + | ==Example Application== |
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| + | *NXP MCX-N9XX-EVK evaluation board: https://wiki.segger.com/NXP_MCX-N9XX-EVK#Example_Project |
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| + | --!> |
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Revision as of 13:27, 24 May 2023
Contents
The SemiDrive E32xx are Cortex-R5 based MCUs.
Internal Flash
E32xx devices consist of a SIP and have an internal QSPI flash.
Therefore programming the internal flash requires special handling. For more information about this, please see the QSPI Flash Programming Support article.
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x10000000 | Up to 4 MB | 
|
ECC RAM
E32xx devices have ECC RAM which can be disabled. However, a connect to E32xx devices will initialize 512KB at 0x500000 (1MB at 0x400000 for E3210).
Reset
No device specific reset is necessary. The normal Cortex-R reset is performed.
See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices
