Difference between revisions of "SemiDrive E32xx"
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The SemiDrive E32xx are Cortex-R5 based MCUs. |
The SemiDrive E32xx are Cortex-R5 based MCUs. |
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| + | |||
| + | ==Internal Flash== |
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| + | |||
| + | E32xx devices have no internal flash. |
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| + | |||
| + | ==QSPI Flash== |
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| + | |||
| + | E32xx devices consist of a SIP and have an internal QSPI flash. |
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| + | |||
| + | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| + | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
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| + | {| class="seggertable" |
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| + | |- |
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| + | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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| + | |- |
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| + | | QSPI flash || 0x10000000 || 128 MB || *'''Default''' CS@X2 SCLK@X1 D0@X3 D1@X4 D2@X5 D3@X6 |
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| + | |} |
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| + | |||
| + | ==ECC RAM== |
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| + | E32xx devices have ECC RAM which can be disabled. |
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| + | However, a connect to E32xx devices will initialize 512KB at 0x500000 (1MB at 0x400000 for E3210). |
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| + | |||
| + | ==Reset== |
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| + | No device specific reset is necessary. The normal Cortex-R reset is performed. |
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| + | |||
| + | See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices |
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Revision as of 13:54, 24 May 2023
Contents
The SemiDrive E32xx are Cortex-R5 based MCUs.
Internal Flash
E32xx devices have no internal flash.
QSPI Flash
E32xx devices consist of a SIP and have an internal QSPI flash.
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| QSPI flash | 0x10000000 | 128 MB | *Default CS@X2 SCLK@X1 D0@X3 D1@X4 D2@X5 D3@X6 |
ECC RAM
E32xx devices have ECC RAM which can be disabled. However, a connect to E32xx devices will initialize 512KB at 0x500000 (1MB at 0x400000 for E3210).
Reset
No device specific reset is necessary. The normal Cortex-R reset is performed.
See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Strategies_for_ARMv8-AR_devices
